SNVSAN3F August   2017  – November 2020 LMR33630

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 System Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power-Good Flag Output
      2. 8.3.2 Enable and Start-up
      3. 8.3.3 Current Limit and Short Circuit
      4. 8.3.4 Undervoltage Lockout and Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Auto Mode
      2. 8.4.2 Dropout
      3. 8.4.3 Minimum Switch On-Time
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design With WEBENCH® Tools
        2. 9.2.2.2  Choosing the Switching Frequency
        3. 9.2.2.3  Setting the Output Voltage
        4. 9.2.2.4  Inductor Selection
        5. 9.2.2.5  Output Capacitor Selection
        6. 9.2.2.6  Input Capacitor Selection
        7. 9.2.2.7  CBOOT
        8. 9.2.2.8  VCC
        9. 9.2.2.9  CFF Selection
        10. 9.2.2.10 External UVLO
        11. 9.2.2.11 Maximum Ambient Temperature
      3. 9.2.3 Application Curves
    3. 9.3 What to Do and What Not to Do
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Ground and Thermal Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RNX|12
  • DDA|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

GUID-42F5E693-63C1-4EE1-85CC-208D8519F85F-low.svgFigure 6-1 DDA Package8-Pin HSOIC With PowerPAD™Top View
GUID-0E02D1BA-E3C2-46B7-9AD2-CA62652B85EF-low.svgFigure 6-2 RNX Package12-Pin VQFNTop View
Table 6-1 Pin Functions
PIN TYPE DESCRIPTION
HSOIC VQFN NAME
1 1,11 PGND G Power ground terminal. Connect to system ground and AGND. Connect to bypass capacitor with short wide traces.
2 2,10 VIN P Input supply to regulator. Connect a high-quality bypass capacitor or capacitors directly to this pin and PGND.
3 9 EN A Enable input to regulator. High = ON, low = OFF. Can be connected directly to VIN; Do not float.
4 8 PG A Open drain power-good flag output. Connect to suitable voltage supply through a current limiting resistor. High = power OK, low = power bad. Flag pulls low when EN = Low. Can be left open when not used.
5 7 FB A Feedback input to regulator. Connect to tap point of feedback voltage divider. Do not float. Do not ground.
6 5 VCC P Internal 5-V LDO output. Used as supply to internal control circuits. Do not connect to external loads. Can be used as logic supply for power-good flag. Connect a high-quality 1-µF capacitor from this pin to GND.
7 4 BOOT P Boot-strap supply voltage for internal high-side driver. Connect a high-quality 100-nF capacitor from this pin to the SW pin. On the VQFN package connect the SW pin to NC on the PCB. This simplifies the connection from the CBOOT capacitor to the SW pin.
8 12 SW P Regulator switch node. Connect to power inductor. On the VQFN package connect the SW pin to NC on the PCB. This simplifies the connection from the CBOOT capacitor to the SW pin.
THERMAL
PAD		 6 AGND G Analog ground for regulator and system. Ground reference for internal references and logic. All electrical parameters are measured with respect to this pin. Connect to system ground on PCB. For the HSOIC package, the pad on the bottom of the device serves as both the AGND connection and a thermal connection to the heat sink ground plane. This pad must be soldered to a ground plane to achieve good electrical and thermal performance.
— 3 NC — On the VQFN package the SW pin must be connected to NC on the PCB. This simplifies the connection from the CBOOT capacitor to the SW pin. This pin has no internal connection to the regulator.
A = Analog, P = Power, G = Ground