SNVSB91C July   2019  – June 2020 LMR36506-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Efficiency versus Output Current VOUT = 3.3 V (Fixed), 2.2 MHz
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD (Automotive) Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 System Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Enable, Start-up and Shutdown
      2. 8.3.2  External CLK SYNC (with MODE/SYNC)
        1. 8.3.2.1 Pulse-Dependent MODE/SYNC Pin Control
      3. 8.3.3  Adjustable Switching Frequency (with RT)
      4. 8.3.4  Power-Good Output Operation
      5. 8.3.5  Internal LDO, VCC UVLO, and VOUT/BIAS Input
      6. 8.3.6  Bootstrap Voltage and VCBOOT-UVLO (CBOOT Terminal)
      7. 8.3.7  Output Voltage Selection
      8. 8.3.8  Spread Spectrum
      9. 8.3.9  Soft Start and Recovery from Dropout
        1. 8.3.9.1 Recovery from Dropout
      10. 8.3.10 Current Limit and Short Circuit
      11. 8.3.11 Thermal Shutdown
      12. 8.3.12 Input Supply Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
        1. 8.4.3.1 CCM Mode
        2. 8.4.3.2 Auto Mode - Light Load Operation
          1. 8.4.3.2.1 Diode Emulation
          2. 8.4.3.2.2 Frequency Reduction
        3. 8.4.3.3 FPWM Mode - Light Load Operation
        4. 8.4.3.4 Minimum On-time (High Input Voltage) Operation
        5. 8.4.3.5 Dropout
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Choosing the Switching Frequency
        2. 9.2.2.2 Setting the Output Voltage
          1. 9.2.2.2.1 FB for Adjustable Output
        3. 9.2.2.3 Inductor Selection
        4. 9.2.2.4 Output Capacitor Selection
        5. 9.2.2.5 Input Capacitor Selection
        6. 9.2.2.6 CBOOT
        7. 9.2.2.7 VCC
        8. 9.2.2.8 CFF Selection
          1. 9.2.2.8.1 External UVLO
        9. 9.2.2.9 Maximum Ambient Temperature
      3. 9.2.3 Application Curves
    3. 9.3 What to Do and What Not to Do
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground and Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.4 Power-Good Output Operation

The power-good feature using the PG pin of the LMR36506-Q1 can be used to reset a system microprocessor whenever the output voltage is out of regulation. This open-drain output remains low under device fault conditions, such as current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents false flag operation for any short duration excursions in the output voltage, such as during line and load transients. Output voltage excursions lasting less than tRESET_FILTER do not trip the power-good flag. Power-good operation can best be understood in reference to Figure 14. Table 3 gives a more detailed breakdown the PGOOD operation. Here, VPG-UV is defined as the PG-UV scaled version of the VOUT-Reg (target regulated output voltage) and VPG-HYS as the PG-HYS scaled version of the VOUT-Reg, where both PG-UV and PG-HYS are listed in the Electrical Characteristics. During the initial power up, a total delay of 5 ms (typ.) is encountered from the time the VEN-VOUT is triggered to the time that the power-good is flagged high. This delay only occurs during the device start-up and is not encountered during any other normal operation of the power-good function. When EN is pulled low, the power-good flag output is also forced low. With EN low, power-good remains valid as long as the input voltage (VPG-VALID is ≥ 1 V (typical).

The power-good output scheme consists of an open-drain n-channel MOSFET, which requires an external pullup resistor connected to a suitable logic supply. It can also be pulled up to either VCC or VOUT through an appropriate resistor, as desired. If this function is not needed, the PGOOD pin must be grounded. Limit the current into this pin to ≤ 4 mA.

LMR36506-Q1 PGOODwdelay.gifFigure 14. Power-Good Operation (OV Events Not Included)

Table 3. Fault Conditions for PGOOD (Pull Low)

FAULT CONDITION INITIATED FAULT CONDITION ENDS (AFTER WHICH tPGOOD_ACT MUST PASS BEFORE PGOOD OUTPUT IS RELEASED)
VOUT < VPG-UV AND t > tRESET_FILTER Output voltage in regulation:
VPG-UV + VPG-HYS < VOUT < VPG-OV - VPG-HYS
VOUT > VPG-OV AND t > tRESET_FILTER Output voltage in regulation
TJ > TSD-R TJ < TSD-F AND output voltage in regulation
EN < VEN-VOUT - VEN-HYST EN > VEN-VOUT AND output voltage in regulation
VCC < VCC-UVLO - VCC-UVLO-HYST VCC > VCC-UVLO AND output voltage in regulation