SNAS714C November   2016  – August 2021 LMS3635-Q1 , LMS3655-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Tables
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Thermal Information (for Device Mounted on PCB)
    6. 7.6 Electrical Characteristics
    7. 7.7 System Characteristics
    8. 7.8 Timing Requirements
    9. 7.9 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
      1. 8.2.1 Control Scheme
    3. 8.3 Feature Description
      1. 8.3.1 RESET Flag Output
      2. 8.3.2 Enable and Start-Up
      3. 8.3.3 Soft-Start Function
      4. 8.3.4 Current Limit
      5. 8.3.5 Hiccup Mode
      6. 8.3.6 Synchronizing Input
      7. 8.3.7 Undervoltage Lockout (UVLO) and Thermal Shutdown (TSD)
      8. 8.3.8 Input Supply Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 AUTO Mode
      2. 8.4.2 FPWM Mode
      3. 8.4.3 Dropout
      4. 8.4.4 Spread-Spectrum Operation
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 General Application
        1. Design Requirements
        2. Detailed Design Procedure
          1. Custom Design With WEBENCH® Tools
          2. External Components Selection
            1. Input Capacitors
            2. Output Inductors and Capacitors
              1. Inductor Selection
              2. Output Capacitor Selection
          3. Setting the Output Voltage
          4. FB for Adjustable Output
          5. VCC
          6. BIAS
          7. CBOOT
          8. Maximum Ambient Temperature
        3. Application Curves
      2. 9.2.2 Fixed 5-V Output for USB-Type Applications
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      3. 9.2.3 Fixed 3.3-V Output
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      4. 9.2.4 6-V Adjustable Output
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
    3. 9.3 Do's and Don't's
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Current Limit

The LMS36x5-Q1 incorporates a valley current limit for normal overloads and for short-circuit protection. A precision low-side current limit prevents excessive average output current from the buck converter of the LMS36x5-Q1. A high-side peak-current limit is employed for protection of the top N MOSFET and inductors. The two current limits enable use of smaller inductors than a system with a single current limit. This scheme allows use of inductors with saturation current rated less than twice the operating current of the LMS36x5-Q1.

During overloads the low-side current limit, IL-LS (see Section 7.6), determines the maximum load current that the LMS36x5-Q1 can supply. When the low-side switch turns on, the inductor current begins to ramp down. If the current does not fall below IL-LS before the next turnon cycle, then that cycle is skipped, and the low-side FET is left on until the current falls below IL-LS. This is different than the more typical peak current limit, and results in Equation 1 for the maximum load current.

Equation 1. GUID-0BC53C77-3577-4BF0-9DBD-E6FE5949AF2B-low.gif

If the converter continues triggering valley current limit for more than about 64 clock cycles, the device turns off both high and low side switches for approximately 6 ms (see TW in Section 7.8). If the overload is still present after the hiccup time, another 64 cycles is counted, and the process is repeated. If the current limit is not tripped for two consecutive clock cycles, the counter is reset. The hiccup time allows the inductor current to fall to zero, resetting the inductor volt-second balance. Of course the output current is greatly reduced in this condition . A typical short-circuit transient and recovery is shown in Figure 8-5.

GUID-FA880CC5-ABEE-4595-872B-4938F18BF4D2-low.pngFigure 8-5 Short-Circuit Transient and Recovery

The high-side current limit trips when the peak inductor current reaches IL-HS (see Section 7.6). This is a cycle-by-cycle current limit and does not produce any frequency or current foldback. It is meant to protect the high-side MOSFET from excessive current. Under some conditions, such as high input voltage, this current limit may trip before the low-side protection. The peak value of this current limit varies with duty cycle.

In response to a short circuit, the peak current limit prevents excessive peak current while valley current limit prevents excessive average inductor current and keeps the power dissipation low during a fault. After a small number of cycles of valley current limit triggers, hiccup mode is activated.

In addition, the INEG current limit also protects the low-side switch from excessive negative current when the device is in FPWM mode. If this current exceeds INEG, the low-side switch is turned off until the next clock cycle. When the device is in AUTO mode, the negative current limit is increased to about IZC (about 0 A). This allows the device to operate in DCM.