BIAS is connected to the output. This example assumes that inductive shorts are a risk for this application so a 3-Ω resistor is added between BIAS and the output. A 0.1-µF capacitor is added close to the BIAS pin.
FB is connected to the output through a voltage divider in order to create a voltage of 1 V at the FB pin when the output is at 6 V. A 22-pF capacitance is added in parallel with the top feedback resistor in order to improve transient behavior. BIAS and FB are connected to the output through separate traces. This is important to reduce noise and achieve good performances. See Layout Guidelines for more details on the proper layout method.
SYNC is connected to ground directly as there is no need for this function in this application.
EN is toggled by an external device (like an MCU for example). A pulldown resistor is placed to ensure the part does not turn on if the external source is not driving the pin (Hi-Z condition).
FPWM is connected to VIN. This causes the device to operate in FPWM mode. To prevent frequency foldback behavior at low duty cycles, provide a 200mA load. In this mode, the device remains in CCM operation regardless of the output current and is ensured to be within the boundaries set by FSW. The drawback is that the efficiency is not optimized for light loads. SeeDevice Functional Modes for more details.
A 4.7-µF capacitor is connected between VCC and GND close to the VCC pin. This ensure stable operation of the internal LDO.
RESET is not used in this example so the pin has been left floating. Other possible connections can be seen in the previous typical applications and in RESET Flag Output.