SNAS800B July   2021  – February 2024 LMX1204

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Range of Dividers and Multiplier
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power On Reset
      2. 6.3.2 Temperature Sensor
      3. 6.3.3 Clock Outputs
        1. 6.3.3.1 Clock Output Buffers
        2. 6.3.3.2 Clock MUX
        3. 6.3.3.3 Clock Divider
        4. 6.3.3.4 Clock Multiplier and Filter Modes
          1. 6.3.3.4.1 General Information About the Clock Multiplier
          2. 6.3.3.4.2 State Machine Clock for the Clock Multiplier
            1. 6.3.3.4.2.1 State Machine Clock
          3. 6.3.3.4.3 Calibration for the Clock Multiplier
          4. 6.3.3.4.4 Using the x1 Clock Multiplier as a Filter
          5. 6.3.3.4.5 Lock Detect for the Clock Multiplier
      4. 6.3.4 Device Functional Modes Configurations
      5. 6.3.5 LOGICLK Output
        1. 6.3.5.1 LOGICLK Output Format
        2. 6.3.5.2 LOGICLK_DIV_PRE and LOGICLK_DIV Dividers
      6. 6.3.6 SYSREF
        1. 6.3.6.1 SYSREF Output Buffers
          1. 6.3.6.1.1 SYSREF Output Buffers for Main Clocks (SYSREFOUT)
          2. 6.3.6.1.2 SYSREF Output Buffer for LOGICLK
        2. 6.3.6.2 SYSREF Frequency and Delay Generation
        3. 6.3.6.3 SYSREFREQ pins and SYSREFREQ_SPI Field
          1. 6.3.6.3.1 SYSREFREQ Pins Common-Mode Voltage
          2. 6.3.6.3.2 SYSREFREQ Windowing Feature
            1. 6.3.6.3.2.1 General Procedure Flowchart for SYSREF Windowing Operation
            2. 6.3.6.3.2.2 SYSREFREQ Repeater Mode With Delay Gen (Retime)
      7. 6.3.7 SYNC Feature
    4. 6.4 Device Functional Modes
  8. 7 Register Map
    1. 7.1 LMX1204 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 SYSREFREQ Input Configuration
      2. 8.1.2 Reducing SYSREF Common Mode Voltages
      3. 8.1.3 Current Consumption
      4. 8.1.4 Treatment of Unused Pins
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions



Figure 4-1 RHA Package40-Pin VQFNTop View
Table 4-1 Pin Functions
NAME NO. TYPE(1) DESCRIPTION
BIAS01 20 BYP If not using the multiplier, this pin can be left open. If using the multiplier, bypass this pin to GND with a 10-nF capacitor for optimal noise performance.
BIAS23 31 BYP If not using the multiplier, this pin can be left open. If using the multiplier, bypass this pin to GND with a 10-µF and 0.1-µF capacitor for optimal noise performance.
CLKIN_N 7 I Differential reference input clock. Internal 50-Ω termination. AC-couple with a capacitor appropriate to the input frequency (typically 0.1 µF or smaller). If using single-ended, terminate unused side with a series AC-coupling capacitor 50-Ω resistor to GND.
CLKIN_P 6
CLKOUT0_N 15 O Differential clock output pairs. Each pin is an open-collector output with internally integrated 50-Ω resistor with programmable output swing. AC coupling required.
CLKOUT0_P 14
CLKOUT1_N 19
CLKOUT1_P 18
CLKOUT2_N 32
CLKOUT2_P 33
CLKOUT3_N 36
CLKOUT3_P 37
CS# 10 I SPI chip select. High impedance CMOS input. Accepts up to 3.3 V.
DAP DAP GND Ground these pins.
GND 5,13,17,26,34,38
LOGICLKOUT_N 27 O Differential clock output pair. Selectable CML, LVDS, or LVPECL format. Programmable common-mode voltage.
LOGICLKOUT_P 28
LOGISYSREFOUT_N 23 O Differential clock output pair. Selectable CML, LVDS, or LVPECL format. Programmable common-mode voltage.
LOGISYSREFOUT_P 24
MUXOUT 1 O Multiplexed pin serial data readback and lock status of the multiplier.
SCK 8 I SPI clock. High impedance CMOS input. Accepts up to 3.3 V.
SDI 9 I SPI data input. High impedance CMOS input. Accepts up to 3.3 V.
SYSREFREQ_N 3 I Differential SYSREF request input for JESD204B support. Internal 50-Ω AC coupled to internal common-mode voltage or capacitor to GND. Supports AC and DC coupling which can directly accept a common mode voltage of 1.2 to 2 V.
SYSREFREQ_P 2
SYSREFOUT0_N 12 O Differential SYSREF CML output pairs for JESD204B support. Supports AC and DC coupling with programmable common-mode voltage of 0.6 to 2 volts.
SYSREFOUT0_P 11
SYSREFOUT1_N 22
SYSREFOUT1_P 21
SYSREFOUT2_N 29
SYSREFOUT2_P 30
SYSREFOUT3_N 39
SYSREFOUT3_P 40
VCC_CLKIN 4 PWR Connect to a 2.5-V supply. Recommend a shunt high frequency capacitor (typically 0.1 µF or smaller) close to the pin in parallel with larger capacitors (typically 1 µF and 10 µF) farther away.
VCC_LOGICLK 25
VCC01 16
VCC23 35
(1) I = Input, O = Output, GND = Ground, PWR = Power, BYP = Bypass