SNAS800 July   2021 LMX1204

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Range of Dividers and Multiplier
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power On Reset
      2. 7.3.2 Clock Outputs
        1. 7.3.2.1 Clock Output Buffers
        2. 7.3.2.2 Clock MUX
        3. 7.3.2.3 Clock Divider
        4. 7.3.2.4 Clock Multiplier
      3. 7.3.3 SYSREF
        1. 7.3.3.1 SYSREF Output Buffers
          1. 7.3.3.1.1 SYSREF Output Buffer for Main Clocks
          2. 7.3.3.1.2 SYSREF Output Buffer for LOGICLK
        2. 7.3.3.2 SYSREF Frequency and Delay Generation
        3. 7.3.3.3 SYSREFREQ pins
          1. 7.3.3.3.1 SYSREFREQ Pins Common Mode Voltage
          2. 7.3.3.3.2 SYSREFREQ Pin Windowing Feature
        4. 7.3.3.4 SYNC Feature
      4. 7.3.4 LOGICLK Output
        1. 7.3.4.1 LOGICLK Output Format
        2. 7.3.4.2 LOGICLK_DIV_PRE and LOGICLK_DIV Dividers
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Applications Information
      1. 8.1.1 Current Consumption
      2. 8.1.2 Treatment of Unused Pins
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Timing Requirements

MIN NOM MAX UNIT
Timing Requirements
fSPIReadBack SPI readback speed 1/(tCWL + tCWH) 2 MHz
tCE Clock to enable low time 20 ns
tCS Clock to data wait time 20 ns
tCH Clock to data hold time 20 ns
tCWH Clock pulse width high 100 ns
tCWL Clock pulse width low 100 ns
tCES Enable to clock setup time 20 ns
tEWH Enable pulse width high 50 ns
tCD Falling clock edge to data wait time 100 ns