SNAS800 July   2021 LMX1204

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Range of Dividers and Multiplier
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power On Reset
      2. 7.3.2 Clock Outputs
        1. 7.3.2.1 Clock Output Buffers
        2. 7.3.2.2 Clock MUX
        3. 7.3.2.3 Clock Divider
        4. 7.3.2.4 Clock Multiplier
      3. 7.3.3 SYSREF
        1. 7.3.3.1 SYSREF Output Buffers
          1. 7.3.3.1.1 SYSREF Output Buffer for Main Clocks
          2. 7.3.3.1.2 SYSREF Output Buffer for LOGICLK
        2. 7.3.3.2 SYSREF Frequency and Delay Generation
        3. 7.3.3.3 SYSREFREQ pins
          1. 7.3.3.3.1 SYSREFREQ Pins Common Mode Voltage
          2. 7.3.3.3.2 SYSREFREQ Pin Windowing Feature
        4. 7.3.3.4 SYNC Feature
      4. 7.3.4 LOGICLK Output
        1. 7.3.4.1 LOGICLK Output Format
        2. 7.3.4.2 LOGICLK_DIV_PRE and LOGICLK_DIV Dividers
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Applications Information
      1. 8.1.1 Current Consumption
      2. 8.1.2 Treatment of Unused Pins
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Current Consumption
ICC Supply Current (1) Powered up, all outputs  and SYSREF on 1260 mA
Powered up, all outputs on, all SYSREF off 625
Powered up, all outputs and SYSREF off 265
Powered down 10
SYSREF
fSYSREF SYSREF output frequency Generator mode 400 MHz
Repeater mode 100 MHz
Δt SYSREF delay step size fCLKIN = 12.8 GHz 3 ps
tRISE Rise time SYSOUT 45 ps
LOGISYSOUT CML 120 ps
LVDS 120 ps
LVPECL 170 ps
tFALL Fall time SYSOUT 45 ps
LOGISYSOUT CML 120 ps
LVDS 120 ps
LVPECL  170 ps
VOD Differential output voltage SYSOUT 0.85 V
LOGISYSOUT CML 0.4 V
LVDS 0.4 V
LVPECL 0.8 V
VSYSREFCM Common-mode voltage For min, SYSOUTx_PWR=5.  For max SYSOUTx_PWR=2. 0.8 V
SYSREFREQ Pin
VSYSREFIN Voltage input range Differential, DC-coupled
Set externally
0.8 2 Vpp
VCM Input common mode Differential, AC-coupled
Set Internally 
1.2 1.3 2 V
Clock Input
fIN Input frequency 0.3 12.8 GHz
PIN Input power Single-ended power between CLKIN_P or CLKIN_N 0 10 dBm
Clock Outputs
fOUT Output frequency Divide-by-2 0.15 6.4 GHz
fOUT Output frequency Bypass 0.3 12.8
fOUT Output frequency x2, x3, x4 3.2 6.4
fOUT Output frequency LOGICLK output 1 800 MHz
tCAL Calibration-time Multiplier calibration time fIN = 3.2 GHz; x2 700 μs
pOUT Output power OUTx_PWR = 7 fCLKLOUT=12.8 GHz 4 dBm
tRISE Rise time fCLKOUT = 300 MHz 45 ps
tFALL Fall time fCLKOUT = 300 MHz 45 ps
Propagation Delay and Skew
tSKEW Skew between outputs CLKOUTx to CLKOUTy, not LOGICLK 5 ps
Noise, Jitter, and Spurs
JCKx Additive jitter Additive Jitter.  12k to 100 MHz integration bandwidth. Bypass Mode 10 fs, rms
x2 16
x3 26
x4 32
Flicker 1/f flicker noise Slew Rate > 8 V/ns, fCLK=1 GHz Bypass -161 dBc/Hz
NF Noise Floor fOUT = 6 GHz; fOffset ≥ 100 MHz Bypass –157.5 dBc/Hz
NF Divide-by-2 –157.5
NF Multiplier (x2,x3,x4) –159.5
H2 Second harmonic fOUT = 6 GHz (differential), Bypass -30 dBc
fOUT = 6 GHz (single-ended), Bypass -15
fOUT = 6 GHz, single-ended, Divide by 2 -17
H1/2 Input clock leakage spur fOUT = 6 GHz (single-ended) x2 (fSPUR = 3 GHz) -45 dBc
H1/3 x3 (fSPUR = 2 GHz) –50
H1/4 x4 (fSPUR = 1.5 GHz) -54 dBc
ISPUR LOGICLK to CLKOUT fSPUR = 300 MHz (single-ended) –60 dBc
Digital Interface (SCK, SDI, CS#, MUXOUT, SYSREFREQ)
VIH High-level input voltage SCK, SDI, CS# 1.4 3.3 V
VIL Low-level input voltage 0 0.4
VOH Low-level output voltage IOH = 5 mA 1.4 Vcc
VOL Low-level output voltage IOL = 5 mA 0.4
IIH High-level input current -40 40 uA
IIL Low-level input current –25 25
Unless Otherwise Stated, fCLKIN=6 GHz,  CLK_MUX=Bypass, All clocks on with OUTx_PWR=7, LOGICLK_DIV_PRE=1, LOGICLK_DIV=2,SRREQ_MODE=1