SNAS800B July   2021  – February 2024 LMX1204

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Range of Dividers and Multiplier
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power On Reset
      2. 6.3.2 Temperature Sensor
      3. 6.3.3 Clock Outputs
        1. 6.3.3.1 Clock Output Buffers
        2. 6.3.3.2 Clock MUX
        3. 6.3.3.3 Clock Divider
        4. 6.3.3.4 Clock Multiplier and Filter Modes
          1. 6.3.3.4.1 General Information About the Clock Multiplier
          2. 6.3.3.4.2 State Machine Clock for the Clock Multiplier
            1. 6.3.3.4.2.1 State Machine Clock
          3. 6.3.3.4.3 Calibration for the Clock Multiplier
          4. 6.3.3.4.4 Using the x1 Clock Multiplier as a Filter
          5. 6.3.3.4.5 Lock Detect for the Clock Multiplier
      4. 6.3.4 Device Functional Modes Configurations
      5. 6.3.5 LOGICLK Output
        1. 6.3.5.1 LOGICLK Output Format
        2. 6.3.5.2 LOGICLK_DIV_PRE and LOGICLK_DIV Dividers
      6. 6.3.6 SYSREF
        1. 6.3.6.1 SYSREF Output Buffers
          1. 6.3.6.1.1 SYSREF Output Buffers for Main Clocks (SYSREFOUT)
          2. 6.3.6.1.2 SYSREF Output Buffer for LOGICLK
        2. 6.3.6.2 SYSREF Frequency and Delay Generation
        3. 6.3.6.3 SYSREFREQ pins and SYSREFREQ_SPI Field
          1. 6.3.6.3.1 SYSREFREQ Pins Common-Mode Voltage
          2. 6.3.6.3.2 SYSREFREQ Windowing Feature
            1. 6.3.6.3.2.1 General Procedure Flowchart for SYSREF Windowing Operation
            2. 6.3.6.3.2.2 SYSREFREQ Repeater Mode With Delay Gen (Retime)
      7. 6.3.7 SYNC Feature
    4. 6.4 Device Functional Modes
  8. 7 Register Map
    1. 7.1 LMX1204 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 SYSREFREQ Input Configuration
      2. 8.1.2 Reducing SYSREF Common Mode Voltages
      3. 8.1.3 Current Consumption
      4. 8.1.4 Treatment of Unused Pins
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Current Consumption
ICC Supply Current (1) Powered up, all outputs  and SYSREF on 1050 mA
Powered up, all outputs on, all SYSREF off 600
Powered up, all outputs and SYSREF off 265
Powered down(2) 11
SYSREF
fSYSREF SYSREF output frequency Generator mode 200 MHz
Repeater mode 100 MHz
Δt SYSREF delay step size fCLKIN = 12.8 GHz 3 ps
tRISE Rise time (20% to 80%) SYSREFOUT 45 ps
LOGISYSREFOUT CML 120 ps
LVDS 120 ps
LVPECL 230 ps
tFALL Fall time (20% to 80%) SYSREFOUT 45 ps
LOGISYSREFOUT CML 120 ps
LVDS 120 ps
LVPECL  170 ps
VOD Differential output voltage SYSREFOUT 0.85 Vpp
LOGISYSREFOUT CML 0.4 Vp
LVDS 0.4 Vp
LVPECL 0.8 Vp
VSYSREFCM Common mode voltage SYSREFOUT CML
SYSREFOUTx_PWR=4
100 Ω Differential Load		 0.8 V
SYSREFREQ Pins
VSYSREFIN Voltage input range AC differential voltage 0.8 2 Vpp
VCM Input common mode Differential 100 Ω Termination, DC coupled
Set externally		 1.2 1.3 2 V
Clock Input
fIN Input frequency 0.3 12.8 GHz
PIN Input power Single-ended power at CLKIN_P or CLKIN_N 0 10 dBm
Clock Outputs
fOUT Output frequency Divide-by-2 0.15 6.4 GHz
fOUT Output frequency Buffer Mode 0.3 12.8
fOUT Output frequency x1 (filter mode) , x2, x3, x4 3.2 6.4
fOUT Output frequency LOGICLK output 1 800 MHz
tCAL Calibration-time Multiplier calibration time fIN = 3.2 GHz; x2
fSMCLK = 28 MHz		 750 μs
pOUT Output power
Single-Ended

 fCLKLOUT= 6 GHz
OUTx_PWR = 7		 4 dBm
tRISE Rise time (20% to 80%) fCLKOUT = 300 MHz 45 ps
tFALL Fall time (20% to 80%) fCLKOUT = 300 MHz 45 ps
Propagation Delay and Skew
| tSKEW | Magnitude of skew between outputs CLKOUTx to CLKOUTy, not LOGICLK 1 15 ps
Noise, Jitter, and Spurs
JCKx Additive jitter Additive Jitter.  12k to 100 MHz integration bandwidth. Buffer Mode 5 fs, rms
Filter Mode 12
x2 Multiplier 16
x3 Multiplier 21
x4 Multiplier 26
Flicker 1/f flicker noise Slew Rate > 8 V/ns, fCLK = 6 GHz
Buffer Mode

 -154 dBc/Hz
NF Noise Floor fOUT = 6 GHz; fOffset ≥ 100 MHz
Buffer Mode

 -161 dBc/Hz
NF Divide-by-2 -160.5
NF Multiplier (x1, x2,x3,x4) –161.5
NFL Noise Floor LOGICLK output, 300 MHz CML -150.5 dBc/Hz
NFL LVDS -151.5
NFL LVPECL -153.5
H2 Second harmonic fOUT = 6 GHz (differential), Buffer Mode -25 dBc
fOUT = 6 GHz (single-ended), Buffer Mode -13
fOUT = 6 GHz, single-ended, Divide by 2 -16
H1/2 Input clock leakage spur fOUT = 6 GHz (single-ended) x2 (fSPUR = 3 GHz) -40 dBc
H1/3 x3 (fSPUR = 2 GHz) –50
H1/4 x4 (fSPUR = 1.5 GHz) -54 dBc
ISPUR LOGICLK to CLKOUT fSPUR = 300 MHz (differential) –70 dBc
Digital Interface (SCK, SDI, CS#, MUXOUT)
VIH High-level input voltage SCK, SDI, CS# 1.4 3.3 V
VIL Low-level input voltage 0 0.4
VOH High-level output voltage IOH = 5 mA 1.4 Vcc
IOH = 0.1 mA 2.2 Vcc
VOL Low-level output voltage IOL = 5 mA 0.45
IIH High-level input current -42 42 uA
IIL Low-level input current –25 25
(1) Unless Otherwise Stated, fCLKIN=6 GHz,  CLK_MUX=Buffer, All clocks on with OUTx_PWR=7, SYSREFREQ_MODE=1
(2) For powered down mode, if the LOGISYSREFOUT field is set to LVPECL mode AND the LVPECL resistors are placed, this powerdown current increases to approximately 40 mA.