SNAS680E December   2015  – August 2022 LMX2582

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Functional Description
      1. 7.3.1  Input Signal
      2. 7.3.2  Input Signal Path
      3. 7.3.3  PLL Phase Detector and Charge Pump
      4. 7.3.4  N Divider and Fractional Circuitry
      5. 7.3.5  Voltage Controlled Oscillator
      6. 7.3.6  VCO Calibration
      7. 7.3.7  Channel Divider
      8. 7.3.8  Output Distribution
      9. 7.3.9  Output Buffer
      10. 7.3.10 Phase Adjust
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down
      2. 7.4.2 Lock Detect
      3. 7.4.3 Register Readback
    5. 7.5 Programming
      1. 7.5.1 Recommended Initial Power on Programming Sequence
      2. 7.5.2 Recommended Sequence for Changing Frequencies
    6. 7.6 Register Maps
      1. 7.6.1 LMX2582 Register Map – Default Values
        1. 7.6.1.1 Register Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Optimization of Spurs
        1. 8.1.1.1 Understanding Spurs by Offsets
        2. 8.1.1.2 Spur Mitigation Techniques
      2. 8.1.2  Configuring the Input Signal Path
        1. 8.1.2.1 Input Signal Noise Scaling
      3. 8.1.3  Input Pin Configuration
      4. 8.1.4  Using the OSCin Doubler
      5. 8.1.5  Using the Input Signal Path Components
        1. 8.1.5.1 Moving Phase Detector Frequency
        2. 8.1.5.2 Multiplying and Dividing by the Same Value
      6. 8.1.6  Designing for Output Power
      7. 8.1.7  Current Consumption Management
      8. 8.1.8  Decreasing Lock Time
      9. 8.1.9  Modeling and Understanding PLL FOM and Flicker Noise
      10. 8.1.10 External Loop Filter
    2. 8.2 Typical Application
      1. 8.2.1 Design for Low Jitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHA|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

3.15 V ≤ VCC ≤ 3.45 V, –40°C ≤ TA ≤ 85°C.
Typical values are at VCC = 3.3 V, 25°C (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
POWER SUPPLY
VCCSupply voltage3.3V
ICCSupply currentSingle 5.4-GHz, 0-dBm output(1)250mA
IPDPowerdown current3.7mA
OUTPUT CHARACTERISTICS
FoutOutput frequency205500MHz
PoutTypical high output powerOutput = 3 GHz, 50-Ω pullup, single-ended(2)8dBm
INPUT SIGNAL PATH
REFinReference input frequency51400MHz
REFvReference input voltageAC-coupled, differential(3)0.22Vppd
MULinInput signal path multiplier input frequency4070MHz
MULoutInput signal path multiplier output frequency180250MHz
PHASE DETECTOR AND CHARGE PUMP
PDFPhase detector frequency5200MHz
Extended range mode(4)0.25400MHz
CPICharge pump currentProgrammable012mA
PLL PHASE NOISE
PLL_flicker_NormNormalized PLL Flicker Noise(5)–126dBc/Hz
PLL_FOMNormalized PLL Noise Floor (PLL Figure of Merit)(5)–231dBc/Hz
VCO
|ΔTCL|Allowable temperature drift(6)VCO not being recalibrated125°C
PNopen loopOutput = 900 MHz10 kHz–105.7dBc/Hz
100 kHz–129.8
1 MHz–150.4
10 MHz-160.6
100 MHz–161.1
Output = 1.8 GHz10 kHz–99.5
100 kHz–123.6
1 MHz–144.5
10 MHz–157.2
100 MHz–157.7
Output = 5.5 GHz10 kHz–89.7
100 kHz–114.0
1 MHz–134.9
10 MHz–151.3
100 MHz–153.3
HD2 2nd Order Harmonic Distortion(7) Testing output A, output at 5 GHz, output power level at 8.5-dBm, single-ended output, other end terminated with 50 Ω. –27 dBc
HD3 3rd Order Harmonic Distortion(7) –25 dBc
DIGITAL INTERFACE
VIHHigh level input voltage1.4VCCV
VILLow level input voltage00.4V
IIHHigh level input current–2525µA
IILLow level input current–2525µA
VOHHigh level output voltageLoad/Source Current of –350 µAVCC – 0.4V
VOLLow level output voltageLoad/Sink Current of 500 µA0.4V
SPIWHighest SPI write speed75MHz
SPIRSPI read speed50MHz
Spur_PFDPhase frequency detector spurPFD = 20 MHz, output = 5.4 GHz–93dBc
(1) For typical total current consumption of 250 mA: 100-MHz input frequency, OSCin doubler bypassed, pre-R divider bypassed, multiplier bypassed, post-R divider bypassed, 100-MHz phase detector frequency, 0.468-mA charge pump current, channel divider off, one output on, 5.4GHz output frequency, 50-Ω output pullup, 0-dBm output power (differential). See the Section 8 section for more information.
(2) For a typical high output power for a single-ended output, with 50-Ω pullup on both M and P side, register OUTx_POW = 63. Un-used side terminated with 50-Ω load.
(3) There is internal voltage biasing so the OSCinM and OSCinP pins must always be AC-coupled (capacitor in series). Vppd is differential peak-to-peak voltage swing. If there is a differential signal (two are negative polarity of each other), the total swing is one subtracted by the other, each should be 0.1 to 1-Vppd. If there is a single-ended signal, it can have 0.2 to 2 Vppd. See the Section 8 section for more information.
(4) To use phase detector frequencies lower than 5-MHz set register FCAL_LPFD_ADJ = 3. To use phase detector frequencies higher than 200 MHz, you must be in integer mode, set register PFD_CTL = 3 (to use single PFD mode), set FCAL_HPFD_ADJ = 3. For more information, see the Section 7 section.
(5) The PLL noise contribution is measured using a clean reference and a wide loop bandwidth and is composed into flicker and flat components. PLL_flat = PLL_FOM + 20 × log(Fvco/Fpd) + 10 × log(Fpd / 1Hz). PLL_flicker (offset) = PLL_flicker_Norm + 20 × log(Fvco / 1GHz) – 10 × log(offset / 10kHz). Once these two components are found, the total PLL noise can be calculated as PLL_Noise = 10 × log(10PLL_Flat / 10 + 10PLL_flicker / 10).
(6) Not tested in production. Ensured by characterization. Allowable temperature drift refers to programming the device at an initial temperature and allowing this temperature to drift without reprogramming the device, and still have the device stay in lock. This change could be up or down in temperature and the specification does not apply to temperatures that go outside the recommended operating temperatures of the device.
(7) This parameter is verified by characterization on evaluation board, not tested in production.