SNAS680D December 2015 – November 2017 LMX2582
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The first step in optimizing spurs is to be able to identify them by offset. Figure 23 gives a good example that can be used to isolate the following spur types.
Based on Figure 23, the most common spurs can be calculated from the frequencies. Note that the % is the modulus operator and is meant to mean the difference to the closest integer multiple. Some examples of how to use this operator are: 36 % 11 = 3, 1000.1 % 50 = 0.1, and 5023.7 % 122.88 = 14.38. Applying this concept, the spurs at various offsets can be identified from Figure 23.
|SPUR TYPE||OFFSET||OFFSET IN Figure 23||COMMENTS|
|OSCin||fOSC||40 MHz||This spur occurs at harmonics of the OSCin frequency.|
|Fpd||fPD||120 MHz||The phase detector spur has many possible mechanisms and occurs at multiples of the phase detector frequency.|
|fOUT % fOSC||fOUT % fOSC||606.25 % 40 = 6.25 MHz||This spur is caused by mixing between the output and input frequencies.|
|fVCO% fOSC||fVCO % fOSC||4850 % 40 = 10 MHz||This spur is caused by mixing between the VCO and input frequencies.|
|fVCO% fPD||fVCO % fPD||4850 % 120 = 50 MHz||This spur would be the same offset as the integer boundary spur if PLL_N_PRE=1, but can be different if this value is greater than one.|
|Integer Boundary||fPD *(Fnum%Fden)/ Fden)||120 × (5%24)/24 = 25 MHz||This is a single spur|
|Primary Fractional||fPD / Fden||120 / 24 = 5 MHz||The primary fractional|
|Sub-Fractional|| fPD / Fden / k
k=2,3, or 6
|First Order Modulator: None
2nd Order Modulator: 120/24/2 = 2.5 MHz
3rd Order Modulator: 120/24/6 = 0.83333 MHz
4th Order Modulator: 120/24/12 = 0.416666 MHz
|To Calculate k:
1st Order Modulator: k=1
2nd Order Modulator: k=1 if Fden is odd, k=2 if Fden is even
3rd Order Modulator: k=1 if Fden not divisible by 2 or 3, k=2 if Fden divisible by 2 not 3, k=3 if Fden divisible by 3 but not 2, Fden = 6 if Fden divisible by 2 and 3
4th Order Modulator: k=1 if Fden not divisible by 2 or 3. k=3 if Fden divisible by 3 but not 2, k=4 if Fden divisible by 2 but not 3, k=12 if Fden divisible by 2 and 3
Sub-Fractional Spurs exist if k>1
In the case that two different spur types occur at the same offset, either name would be correct. Some may name this by the more dominant cause, while others would simply name by choosing the name that is near the top of Table 48.
Once the spur is identified and understood, there will likely be a desire to try to minimize them. Table 49 gives some common methods.
|SPUR TYPE||WAYS TO REDUCE||TRADE-OFF|
|fOUT % fOSC||Use an OSCin signal with low amplitude and high slew rate (like LVDS)|
|fVCO% fPD||Avoid this spur by shifting the phase detector frequency (with the programmable input multiplier or R divider) or shifting the VCO frequency. This spur is better at higher VCO frequency.|
Methods for PLL Dominated Spurs
|Reducing the loop bandwidth may degrade the total integrated noise if the bandwidth is too narrow.|
Methods for VCO Dominated Spurs
|Reducing the phase detector may degrade the phase noise and also reduce the capacitance at the Vtune pin.|
||Decreasing the loop bandwidth too much may degrade in-band phase noise. Also, larger unequivalent fractions only sometimes work|
||Dithering and larger fractions may increase phase noise. MASH_SEED can be set between values 0 and Fden, which changes the sub-fractional spur behavior. This is a deterministic relationship and there will be one seed value that will give best result for this spur.|
The input path is considered the portion of the device between the OSCin pin and the phase detector, which includes the input buffer, R dividers, and programmable multipliers. The way that these are configured can have a large impact on phase noise and fractional spurs.
The input signal noise scales by 20 × log(output frequency / input signal frequency), so always check this to see if the noise of the input signal scaled to the output frequency is close to the PLL in-band noise level. When that happens, the input signal noise is the dominant noise source, not the PLL noise floor.
The OSCinM and OSCinP can be used to support both a single-ended or differential clock. In either configuration, the termination on both sides should match for best common-mode noise rejection. The slew rate and signal integrity of this signal can have an impact on both the phase noise and fractional spurs. Standard clocking types, LVDS, LVPECL, HCSL, and CMOS can all be used.
The lowest PLL flat noise is achieved with a low-noise 200-MHz input signal. If only a low-noise input signal with lower frequency is available (for example a 100-MHz source), you can use the low noise OSCin doubler to attain 200-MHz phase detector frequency. Because PLL_flat = PLL_FOM + 20 × log(Fvco/Fpd) + 10 × log(Fpd / 1Hz), doubling Fpd theoretically gets –6 dB from the 20 × log(Fvco/Fpd) component, +3 dB from the 10 × log(Fpd / 1Hz) component, and cumulatively a –3-dB improvement.
The ideal input is a low-noise, 200-MHz (or multiples of it) signal and 200-MHz phase detector frequency (highest dual PFD frequency). However, if spur mechanisms are understood, certain combinations of the R-divider and Multiplier can help. Refer to the Optimization of Spurs section for understanding spur types and their mechanisms first, then try this section for these specific spurs.
Engaging the multiplier in the reference path allows more flexibility in setting the PFD frequency. One example use case of this is if Fvco % Fpd is the dominant spur. This method can move the PFD frequency and thus the Fvco % Fpd.
Example: Fvco = 3720.12 MHz, Fosc = 300 MHz, Pre-R divider = 5, Fpd = 60 MHz, Fvco%Fosc = 120.12 MHz (Far out), Fvco%Fpd = 120 kHz (dominant). There is a Fvco%Fpd spur at 120 kHz (refer to Figure 27).
Then second case, using divider and multiplier, is Fpd = 53.57 MHz away from 120-kHz spur. Fvco = 3720.12MHz, Fosc = 300MHz, Pre-R divider = 7, Multiplier = 5, Post-R divider = 4, Fpd = 53.57 MHz, Fvco%Fosc = 120.12 MHz (Far out). Fvco % Fpd = 23.79 MHz (far out). There is a 20–dB reduction for the Fvco % Fpd spur at 120 kHz (refer to Figure 28).
Although it may not seem like the first thing to try, the Fvco%Fosc and Fout%Fosc spur can sometimes be improved engaging the OSC_2X bit and then dividing by 2. Although this gives the same phase detector frequency, the spur can be improved.
If there is a desired frequency for highest power, use an inductor pullup and design for the value so that the resonance is at that frequency. Use the formula SRF = 1 / (2π× sqrt[L × C]).
Example: C = 1.4 pF (characteristic). If maximum power is targeted at 1 GHz, L = 18 nH. If maximum power is targeted at 3.3 GHz, L = 1.6 nH
The starting point is the typical total current consumption of 250 mA: 100-MHz input frequency, OSCin doubler bypassed, Pre-R divider bypassed, multiplier bypassed, post-R divider bypassed, 100-MHz phase detector frequency, 0.468-mA charge pump current, channel divider off, one output on, 5400-MHz output frequency, 50-Ω output pullup, 0-dBm output power (differential). To understand current consumption changes due to engaging different functional blocks , refer to Table 50.
|ACTION||STEPS||PROGRAMMING||INCREASE IN CURRENT (mA)|
|Use input signal path||Enable OSCin doubler||OSC_2X = 1||7|
|Enable multiplier||MULT = 3,4,5, or 6||10|
|Add an output||Route VCO to output B||VCO_DISTB_PD = 0||8|
|Enable output B buffer||OUTB_PD = 0||54|
|Increase output power from 0 to +10dBm (differential)||Set highest output buffer current||OUTA_POW = 63||53|
|Use channel divider||Route channel divider to output||CHDIV_DISTA_EN = 1||5|
|Enable channel divider||CHDIV_EN = 1||18|
|Enable chdiv_seg1||CHDIV_SEG1_EN = 1||2|
|Enable chdiv_seg2||CHDIV_SEG2_EN = 1||5|
|Enable chdiv_seg3||CHDIV_SEG3_EN = 1||5|
A calibration time of 590 µs typically to lock to 7-GHz VCO can be achieved with default settings as specified in the Electrical Characteristics table. There are several registers that can be programmed to speed up this time. Lock time consists of the calibration time (time required to calibrate the VCO to the correct frequency range) plus the analog settling time (time lock the PLL in phase and frequency). For fast calibration set registers FCAL_FAST = 1 and ACAL_FAST = 1. Also set the calibration clock frequency [input reference frequency] / 2^CAL_CLK_DIV) to 200 MHz. The 20-µs range lock time can be achieved if the amplitude comparator delay is low, set by register ACAL_CMP_DLY (5 in this example). If this is too low there is not enough time to make the decision of VCO amplitude to use and may result in non-optimal phase noise. The other approach is to turn off amplitude calibration with ACAL_EN=0, then manually choose the amplitude with VCO_IDAC (350 for example). This will also result in 20-µs range calibration time. There are many other registers that can aid calibration time, for example ACAL_VCO_IDAC_STRT lets the user choose what VCO amplitude to start with during amplitude calibration. Setting this value to around 350 will give faster times because it is close to the final amplitude for most final frequencies. FCAL_VCO_SEL_START allows you to choose the VCO core to start with for the calibration instead of starting from core 7 by default. If you know you are locking to a frequency around VCO core 1, you can start from VCO 2 by setting VCO_SEL=2, which should give faster lock times. Go to the Register Maps section for detailed information of these registers and their related registers. For fast analog settling time, design loop filter for very wide loop bandwidth (MHz range).
The calibration sweeps from the top of the VCO frequency range to the bottom. This example does a calibration to lock at 3.7 GHz (which is the worst case). For the left screenshot (Wideband Frequency view), see the sweeping from top to bottom of the VCO range. On the right screenshot (Narrowband Frequency view), see the analog settling time to the precise target frequency.
Follow these recommended settings to design for wide loop bandwidth and extract FOM and flicker noise. The flat model is the PLL noise floor modeled by: PLL_flat = PLL_FOM + 20 × log(Fvco/Fpd) + 10 × log(Fpd / 1 Hz). The flicker noise (also known as 1/f noise) which changes by –10dB / decade, is modeled by: PLL_flicker (offset) = PLL_flicker_Norm + 20 × log(Fvco / 1 GHz) – 10 × log(offset / 10k Hz). The cumulative model is the addition of both components: PLL_Noise = 10*log(10PLL_Flat / 10 + 10PLL_flicker / 10). This is adjusted to fit the the measured data to extract the PLL_FOM and PLL_flicker_Norm spec numbers.
|Charge pump (mA)||12|
|VCO frequency (MHz)||5400|
|Loop bandwidth (kHz)||2000|
|Phase margin (degrees)||30|
|Loop filter (2nd order)|
Refer to the design parameters shown in Table 52.
The integration of phase noise over a certain bandwidth (jitter) is an performance specification that translates to signal-to-noise ratio. Phase noise inside the loop bandwidth is dominated by the PLL, while the phase noise outside the loop bandwidth is dominated by the VCO. As a rule of thumb, jitter is lowest if loop bandwidth is designed to the point where the two intersect. A higher phase margin loop filter design has less peaking at the loop bandwidth and thus lower jitter. The tradeoff with this as longer lock times and spurs should be considered in design as well.