SNAS680D December   2015  – November 2017 LMX2582


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Functional Description
      1. 7.3.1  Input Signal
      2. 7.3.2  Input Signal Path
      3. 7.3.3  PLL Phase Detector and Charge Pump
      4. 7.3.4  N Divider and Fractional Circuitry
      5. 7.3.5  Voltage Controlled Oscillator
      6. 7.3.6  VCO Calibration
      7. 7.3.7  Channel Divider
      8. 7.3.8  Output Distribution
      9. 7.3.9  Output Buffer
      10. 7.3.10 Phase Adjust
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down
      2. 7.4.2 Lock Detect
      3. 7.4.3 Register Readback
    5. 7.5 Programming
      1. 7.5.1 Recommended Initial Power on Programming Sequence
      2. 7.5.2 Recommended Sequence for Changing Frequencies
    6. 7.6 Register Maps
      1. 7.6.1 LMX2582 Register Map - Default Values
        1. Register Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Optimization of Spurs
        1. Understanding Spurs by Offsets
        2. Spur Mitigation Techniques
      2. 8.1.2 Configuring the Input Signal Path
        1. Input Signal Noise Scaling
      3. 8.1.3 Input Pin Configuration
      4. 8.1.4 Using the OSCin Doubler
      5. 8.1.5 Using the Input Signal Path Components
        1. Moving Phase Detector Frequency
        2. Multiplying and Dividing by the Same Value
      6. 8.1.6 Designing for Output Power
      7. 8.1.7 Current Consumption Management
      8. 8.1.8 Decreasing Lock Time
      9. 8.1.9 Modeling and Understanding PLL FOM and Flicker Noise
    2. 8.2 Typical Application
      1. 8.2.1 Design for Low Jitter
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHA|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information


Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
VCC Power supply voltage –0.3 3.6 V
VIN Input voltage to pins other than VCC pins –0.3 VCC + 0.3 V
VOSCin Voltage on OSCin (pin 8 and pin 9) ≤1.8 with VCC Applied ≤1 with VCC= 0 Vpp
TL Lead temperature (solder 4 s) 260 °C
TJ Junction temperature –40 150 °C
Tstg Storage temperature –65 150 °C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±750
Machine model (MM) ESD stress voltage ±250
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2500 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Pins listed as ±1250 V may actually have higher performance.

Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
VCC Power supply voltage 3.15 3.45 V
TA Ambient temperature –40 85 °C
TJ Junction temperature 125 °C

Thermal Information

RθJA Junction-to-ambient thermal resistance 30.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 15.3 °C/W
RθJB Junction-to-board thermal resistance 5.4 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 5.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.9 °C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

Electrical Characteristics

3.15 V ≤ VCC ≤ 3.45 V, –40°C ≤ TA ≤ 85°C.
Typical values are at VCC = 3.3 V, 25°C (unless otherwise noted)
VCC Supply voltage 3.3 V
ICC Supply current Single 5.4-GHz, 0-dBm output(1) 250 mA
IPD Powerdown current 3.7 mA
Fout Output frequency 20 5500 MHz
Pout Typical high output power Output = 3 GHz, 50-Ω pullup, single-ended(2) 8 dBm
REFin Reference input frequency 5 1400 MHz
REFv Reference input voltage AC-coupled, differential(3) 0.2 2 Vppd
MULin Input signal path multiplier input frequency 40 70 MHz
MULout Input signal path multiplier output frequency 180 250 MHz
PDF Phase detector frequency 5 200 MHz
Extended range mode(4) 0.25 400 MHz
CPI Charge pump current Programmable 0 12 mA
PLL_flicker_Norm Normalized PLL Flicker Noise(5) –126 dBc/Hz
PLL_FOM Normalized PLL Noise Floor (PLL Figure of Merit)(5) –231 dBc/Hz
|ΔTCL| Allowable temperature drift(6) VCO not being recalibrated 125 °C
PNopen loop Output = 900 MHz 10 kHz –105.7 dBc/Hz
100 kHz –129.8
1 MHz –150.4
10 MHz -160.6
100 MHz –161.1
Output = 1.8 GHz 10 kHz –99.5
100 kHz –123.6
1 MHz –144.5
10 MHz –157.2
100 MHz –157.7
Output = 5.5 GHz 10 kHz –89.7
100 kHz –114.0
1 MHz –134.9
10 MHz –151.3
100 MHz –153.3
HD2 2nd Order Harmonic Distortion(7) Testing output A, output at 5 GHz, output power level at 8.5-dBm, single-ended output, other end terminated with 50 Ω. –27 dBc
HD3 3rd Order Harmonic Distortion(7) –25 dBc
VIH High level input voltage 1.4 VCC V
VIL Low level input voltage 0 0.4 V
IIH High level input current –25 25 µA
IIL Low level input current –25 25 µA
VOH High level output voltage Load/Source Current of –350 µA VCC – 0.4 V
VOL Low level output voltage Load/Sink Current of 500 µA 0.4 V
SPIW Highest SPI write speed 75 MHz
SPIR SPI read speed 50 MHz
Spur_PFD Phase frequency detector spur PFD = 20 MHz, output = 5.4 GHz –93 dBc
For typical total current consumption of 250 mA: 100-MHz input frequency, OSCin doubler bypassed, pre-R divider bypassed, multiplier bypassed, post-R divider bypassed, 100-MHz phase detector frequency, 0.468-mA charge pump current, channel divider off, one output on, 5.4GHz output frequency, 50-Ω output pullup, 0-dBm output power (differential). See the Application and Implementation section for more information.
For a typical high output power for a single-ended output, with 50-Ω pullup on both M and P side, register OUTx_POW = 63. Un-used side terminated with 50-Ω load.
There is internal voltage biasing so the OSCinM and OSCinP pins must always be AC-coupled (capacitor in series). Vppd is differential peak-to-peak voltage swing. If there is a differential signal (two are negative polarity of each other), the total swing is one subtracted by the other, each should be 0.1 to 1-Vppd. If there is a single-ended signal, it can have 0.2 to 2 Vppd. See the Application and Implementation section for more information.
To use phase detector frequencies lower than 5-MHz set register FCAL_LPFD_ADJ = 3. To use phase detector frequencies higher than 200 MHz, you must be in integer mode, set register PFD_CTL = 3 (to use single PFD mode), set FCAL_HPFD_ADJ = 3. For more information, see the Detailed Description section.
The PLL noise contribution is measured using a clean reference and a wide loop bandwidth and is composed into flicker and flat components. PLL_flat = PLL_FOM + 20 × log(Fvco/Fpd) + 10 × log(Fpd / 1Hz). PLL_flicker (offset) = PLL_flicker_Norm + 20 × log(Fvco / 1GHz) – 10 × log(offset / 10kHz). Once these two components are found, the total PLL noise can be calculated as PLL_Noise = 10 × log(10PLL_Flat / 10 + 10PLL_flicker / 10).
Not tested in production. Ensured by characterization. Allowable temperature drift refers to programming the device at an initial temperature and allowing this temperature to drift without reprogramming the device, and still have the device stay in lock. This change could be up or down in temperature and the specification does not apply to temperatures that go outside the recommended operating temperatures of the device.
This parameter is verified by characterization on evaluation board, not tested in production.

Timing Requirements

3.15 V ≤ VCC ≤ 3.45 V, –40°C ≤ TA ≤ 85°C, except as specified. Typical values are at VCC = 3.3 V, TA = 25°C
tES Clock to enable low time See Figure 1 5 ns
tCS Data to clock setup time 2 ns
tCH Data to clock hold time 2 ns
tCWH Clock pulse width high 5 ns
tCWL Clock pulse width low 5 ns
tCES Enable to clock setup time 5 ns
tEWH Enable pulse width high 2 ns
LMX2582 timing_diagram.gif Figure 1. Serial Data Input Timing Diagram

There are several considerations for programming:

  • A slew rate of at least 30 V/µs is recommended for the CLK, DATA, LE
  • The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the last CLK signal, the data is sent from the shift registers to a register bank
  • The LE pin may be held high after programming and clock pulses are ignored
  • The CLK signal should not be high when LE transitions to low
  • When CLK and DATA lines are shared between devices, TI recommends diving down the voltage to the CLK, DATA, and LE pins closer to the minimum voltage. This provides better noise immunity
  • If the CLK and DATA lines are toggled while the VCO is in lock, as is sometimes the case when these lines are shared with other parts, the phase noise may be degraded during the time of this programming

Typical Characteristics

TA = 25°C (unless otherwise noted)
LMX2582 D001_900M_CL_SNAS680.gif
Figure 2. 900-MHz Output - Closed-Loop Phase Noise
LMX2582 D003_1.8G_CL_SNAS680.gif
Figure 4. 1.8-GHz Output - Closed-Loop Phase Noise
LMX2582 D005_5.5G_CL_SNAS680.gif
Figure 6. 5.5-GHz Output - Closed-Loop Phase Noise
LMX2582 D007_1.8G_jitter_SNAS680.gif
Figure 8. Integrated Jitter (47 fs) - 1.8-GHz Output
LMX2582 D009_1.6G_temp_SNAS680.gif
Figure 10. Variation of Phase Noise Across Temperature
LMX2582 D011_5.5G_outpwr_temp_SNAS680.gif
Figure 12. High Output Power (50-Ω Pullup, Single-Ended)
vs Output Frequency
LMX2582 D013_5.4G_PFDspur_SNAS680_SNAS646_edit.gif
Figure 14. Typical PFD Spur for 5.4-GHz Output
LMX2582 D015_5.4G_chdiv_SNAS680_SNAS646.gif
Figure 16. Impact of Channel Divider Settings
on Phase Noise
LMX2582 D002_900M_OL_SNAS680.gif
Figure 3. 900-MHz Output - Open-Loop Phase Noise
LMX2582 D004_1.8G_OL_SNAS680.gif
Figure 5. 1.8-GHz Output - Open-Loop Phase Noise
LMX2582 D006_5.5G_OL_SNAS680.gif
Figure 7. 5.5-GHz Output - Open-Loop Phase Noise
LMX2582 D008_FOM_5.4G_SNAS680.gif
Figure 9. 5.4-GHz Output Wide Loop Bandwidth –
Showing PLL Performance
LMX2582 D010_1.8G_PSRR_SNAS680.gif
Figure 11. Impact of Supply Ripple
on 1.8-GHz Output Phase Noise
LMX2582 D012_outpwr_code_SNAS680_SNAS646.gif
Figure 13. Output Power at 5.4-GHz Output vs OUTx_POW Code (1 - 31, 48 - 63)
LMX2582 D014_1.8G_locktime_SNAS680.gif
Figure 15. 20-µs Frequency Change Time
to 1.8 GHz With Fast Calibration
LMX2582 D016_5.5G_noisefloor_SNAS680.gif
Figure 17. Noise Floor Variation With Output Frequency