SNAS736C June 2017 – April 2019 LMX2595
The N-divider includes fractional compensation and can achieve any fractional denominator from 1 to (232 – 1). The integer portion of N is the whole part of the N-divider value, and the fractional portion, Nfrac = NUM / DEN, is the remaining fraction. In general, the total N-divider value is determined by N + NUM / DEN. The N, NUM and DEN are software programmable. The higher the denominator, the finer the resolution step of the output. For example, even when using fPD = 200 MHz, the output can increment in steps of 200 MHz / (232 – 1) = 0.047 Hz.Equation 2 shows the relationship between the phase detector and VCO frequencies. Note that in SYNC mode, there is an extra divider that is not shown in Equation 2.
The sigma-delta modulator that controls this fractional division is also programmable from integer mode to fourth order. To make the fractional spurs consistent, the modulator is reset any time that the R0 register is programmed.
The N-divider has minimum value restrictions based on the modulator order and VCO frequency. Furthermore, the PFD_DLY_SEL bit must be programmed in accordance to the Table 2.
|MASH_ORDER||fVCO (MHz)||MINIMUM N||PFD_DLY_SEL|