SNAS739D June   2018  – May 2020 LMX2615-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
      1.      CQFP Package (QFN) Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Reference Oscillator Input
      2. 7.3.2  Reference Path
        1. 7.3.2.1 OSCin Doubler (OSC_2X)
        2. 7.3.2.2 Pre-R Divider (PLL_R_PRE)
        3. 7.3.2.3 Post-R Divider (PLL_R)
      3. 7.3.3  State Machine Clock
      4. 7.3.4  PLL Phase Detector and Charge Pump
      5. 7.3.5  N Divider and Fractional Circuitry
      6. 7.3.6  MUXout Pin
        1. 7.3.6.1 Serial Data Output for Readback
        2. 7.3.6.2 Lock Detect Indicator Set as Type “VCOCal”
        3. 7.3.6.3 Lock Detect Indicator Set as Type “Vtune and VCOCal”
      7. 7.3.7  VCO (Voltage-Controlled Oscillator)
        1. 7.3.7.1 VCO Calibration
        2. 7.3.7.2 Watchdog Feature
        3. 7.3.7.3 RECAL Feature
        4. 7.3.7.4 Determining the VCO Gain
      8. 7.3.8  Channel Divider
      9. 7.3.9  Output Buffer
      10. 7.3.10 Powerdown Modes
      11. 7.3.11 Treatment of Unused Pins
      12. 7.3.12 Phase Synchronization
        1. 7.3.12.1 General Concept
        2. 7.3.12.2 Categories of Applications for SYNC
        3. 7.3.12.3 Procedure for Using SYNC
        4. 7.3.12.4 SYNC Input Pin
      13. 7.3.13 Phase Adjust
      14. 7.3.14 Fine Adjustments for Phase Adjust and Phase SYNC
      15. 7.3.15 SYSREF
        1. 7.3.15.1 Programmable Fields
        2. 7.3.15.2 Input and Output Pin Formats
          1. 7.3.15.2.1 SYSREF Output Format
        3. 7.3.15.3 Examples
        4. 7.3.15.4 SYSREF Procedure
      16. 7.3.16 Pin Modes
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Recommended Initial Power-Up Sequence
      2. 7.5.2 Recommended Sequence for Changing Frequencies
    6. 7.6 Register Maps
      1. 7.6.1 Register Map
        1. 7.6.1.1  R0 Register (Offset = 0x0) [reset = X]
          1. Table 22. R0 Register Field Descriptions
        2. 7.6.1.2  R1 Register (Offset = 0x1) [reset = 0x4]
          1. Table 23. R1 Register Field Descriptions
        3. 7.6.1.3  R8 Register (Offset = 0x8) [reset = X]
          1. Table 24. R8 Register Field Descriptions
        4. 7.6.1.4  R9 Register (Offset = 0x9) [reset = X]
          1. Table 25. R9 Register Field Descriptions
        5. 7.6.1.5  R11 Register (Offset = 0xB) [reset = 0x10]
          1. Table 26. R11 Register Field Descriptions
        6. 7.6.1.6  R12 Register (Offset = 0xC) [reset = 0x1]
          1. Table 27. R12 Register Field Descriptions
        7. 7.6.1.7  R14 Register (Offset = 0xE) [reset = 0x70]
          1. Table 28. R14 Register Field Descriptions
        8. 7.6.1.8  R16 Register (Offset = 0x10) [reset = 0x80]
          1. Table 29. R16 Register Field Descriptions
        9. 7.6.1.9  R19 Register (Offset = 0x13) [reset = 0xB7]
          1. Table 30. R19 Register Field Descriptions
        10. 7.6.1.10 R20 Register (Offset = 0x14) [reset = X]
          1. Table 31. R20 Register Field Descriptions
        11. 7.6.1.11 R31 Register (Offset = 0x1F) [reset = X]
          1. Table 32. R31 Register Field Descriptions
        12. 7.6.1.12 R34 Register (Offset = 0x22) [reset = 0x0]
          1. Table 33. R34 Register Field Descriptions
        13. 7.6.1.13 R36 Register (Offset = 0x24) [reset = 0x46]
          1. Table 34. R36 Register Field Descriptions
        14. 7.6.1.14 R37 Register (Offset = 0x25) [reset = 0x400]
          1. Table 35. R37 Register Field Descriptions
        15. 7.6.1.15 R38 Register (Offset = 0x26) [reset = 0xFD51]
          1. Table 36. R38 Register Field Descriptions
        16. 7.6.1.16 R39 Register (Offset = 0x27) [reset = 0xDA80]
          1. Table 37. R39 Register Field Descriptions
        17. 7.6.1.17 R40 Register (Offset = 0x28) [reset = 0x0]
          1. Table 38. R40 Register Field Descriptions
        18. 7.6.1.18 R41 Register (Offset = 0x29) [reset = 0x0]
          1. Table 39. R41 Register Field Descriptions
        19. 7.6.1.19 R42 Register (Offset = 0x2A) [reset = 0x0]
          1. Table 40. R42 Register Field Descriptions
        20. 7.6.1.20 R43 Register (Offset = 0x2B) [reset = 0x0]
          1. Table 41. R43 Register Field Descriptions
        21. 7.6.1.21 R44 Register (Offset = 0x2C) [reset = 0x1FA3]
          1. Table 42. R44 Register Field Descriptions
        22. 7.6.1.22 R45 Register (Offset = 0x2D) [reset = X]
          1. Table 43. R45 Register Field Descriptions
        23. 7.6.1.23 R46 Register (Offset = 0x2E) [reset = 0x1]
          1. Table 44. R46 Register Field Descriptions
        24. 7.6.1.24 R58 Register (Offset = 0x3A) [reset = X]
          1. Table 45. R58 Register Field Descriptions
        25. 7.6.1.25 R59 Register (Offset = 0x3B) [reset = 0x1]
          1. Table 46. R59 Register Field Descriptions
        26. 7.6.1.26 R60 Register (Offset = 0x3C) [reset = 0x9C4]
          1. Table 47. R60 Register Field Descriptions
        27. 7.6.1.27 R69 Register (Offset = 0x45) [reset = 0x0]
          1. Table 48. R69 Register Field Descriptions
        28. 7.6.1.28 R70 Register (Offset = 0x46) [reset = 0xC350]
          1. Table 49. R70 Register Field Descriptions
        29. 7.6.1.29 R71 Register (Offset = 0x47) [reset = 0x80]
          1. Table 50. R71 Register Field Descriptions
        30. 7.6.1.30 R72 Register (Offset = 0x48) [reset = 0x1]
          1. Table 51. R72 Register Field Descriptions
        31. 7.6.1.31 R73 Register (Offset = 0x49) [reset = 0x3F]
          1. Table 52. R73 Register Field Descriptions
        32. 7.6.1.32 R74 Register (Offset = 0x4A) [reset = 0x0]
          1. Table 53. R74 Register Field Descriptions
        33. 7.6.1.33 R75 Register (Offset = 0x4B) [reset = 0x0]
          1. Table 54. R75 Register Field Descriptions
        34. 7.6.1.34 R110 Register (Offset = 0x6E) [reset = 0x0]
          1. Table 55. R110 Register Field Descriptions
        35. 7.6.1.35 R111 Register (Offset = 0x6F) [reset = 0x0]
          1. Table 56. R111 Register Field Descriptions
        36. 7.6.1.36 R112 Register (Offset = 0x70) [reset = 0x0]
          1. Table 57. R112 Register Field Descriptions
        37. 7.6.1.37 R113 Register (Offset = 0x71) [reset = 0x0]
          1. Table 58. R113 Register Field Descriptions
        38. 7.6.1.38 R114 Register (Offset = 0x72) [reset = 0x26F]
          1. Table 59. R114 Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 OSCin Configuration
      2. 8.1.2 OSCin Slew Rate
      3. 8.1.3 RF Output Buffer Power Control
      4. 8.1.4 RF Output Buffer Pullup
        1. 8.1.4.1 Resistor Pullup
        2. 8.1.4.2 Inductor Pullup
        3. 8.1.4.3 Combination Pullup
      5. 8.1.5 RF Output Treatment for the Complimentary Side
        1. 8.1.5.1 Single-Ended Termination of Unused Output
        2. 8.1.5.2 Differential Termination
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Footprint Example on PCB Layout
    4. 10.4 Radiation Environments
      1. 10.4.1 Total Ionizing Dose
      2. 10.4.2 Single Event Effect
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Engineering Samples
    2. 12.2 Package Mechanical Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6.1 Register Map

Table 19. Complete Register Map Table

REG D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
R0 0 VCO_PHASE_
SYNC		 1 0 0 0 OUT_MUTE FCAL_
HPFD_ADJ		 0 0 1 FCAL_EN MUXOUT_LD_SEL RESET POWERDOWN
R1 0 0 0 0 1 0 0 0 0 0 0 0 1 CAL_CLK_DIV
R2 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0
R3 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0
R4 0 0 0 0 1 1 1 0 0 1 0 0 0 0 1 1
R5 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0
R6 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0
R7 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0
R8 0 VCO_DACISET_FORCE 1 0 VCO_CAPCTRL_FORCE 0 0 0 0 0 0 0 0 0 0 0
R9 0 0 0 OSC_2X 0 1 1 0 0 0 0 0 0 1 0 0
R10 0 0 0 1 0 0 0 0 1 1 0 1 1 0 0 0
R11 0 0 0 0 PLL_R 1 1 0 0 0
R12 0 1 0 1 0 0 0 0 PLL_R_PRE
R13 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R14 0 0 0 1 1 1 1 0 0 CPG 0 0 0 0
R15 0 0 0 0 0 1 1 0 0 1 0 0 1 1 1 1
R16 0 0 0 0 0 0 0 VCO_DACISET
R17 0 0 0 0 0 0 0 1 0 0 1 0 1 1 0 0
R18 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0
R19 0 0 1 0 0 1 1 1 VCO_CAPCTRL
R20 1 1 VCO_SEL VCO_SEL_FORCE 0 0 0 1 0 0 1 0 0 0
R21 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1
R22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
R23 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0
R24 0 0 0 0 0 1 1 1 0 0 0 1 1 0 1 0
R25 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 0
R26 0 0 0 0 1 1 0 1 1 0 1 1 0 0 0 0
R27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
R28 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0
R29 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0
R30 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0
R31 0 SEG1_EN 0 0 0 0 1 1 1 1 1 0 1 1 0 0
R32 0 0 0 0 0 0 1 1 1 0 0 1 0 0 1 1
R33 0 0 0 1 1 1 1 0 0 0 1 0 0 0 0 1
R34 0 0 0 0 0 0 0 0 0 0 0 0 0 PLL_N[18:16]
R35 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
R36 PLL_N[15:0]
R37 1 0 PFD_DLY_SEL 0 0 0 0 0 1 0 0
R38 PLL_DEN[31:16]
R39 PLL_DEN[15:0]
R40 MASH_SEED[31:16]
R41 MASH_SEED[15:0]
R42 PLL_NUM[31:16]
R43 PLL_NUM[15:0]
R44 0 0 OUTA_PWR OUTB_PD OUTA_PD MASH_RESET_N 0 0 MASH_ORDER
R45 1 1 0 OUTA_MUX 0 0 0 1 1 OUTB_PWR
R46 0 0 0 0 0 1 1 1 1 1 1 1 1 1 OUTB_MUX
R47 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
R48 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
R49 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0
R50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R51 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
R52 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0
R53 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R54 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R55 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R56 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R57 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
R58 INPIN_
IGNORE		 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
R59 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LD_
TYPE
R60 LD_DLY
R61 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0
R62 0 0 0 0 0 0 1 1 0 0 1 0 0 0 1 0
R63 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R64 0 0 0 1 0 0 1 1 1 0 0 0 1 0 0 0
R65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R66 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0
R67 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R68 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0
R69 MASH_RST_COUNT[31:16]
R70 MASH_RST_COUNT[15:0]
R71 0 0 0 0 0 0 0 0 SYSREF_DIV_PRE SYSREF_PULSE SYSREF
_EN		 SYSREF_REPEAT 0 0
R72 0 0 0 0 0 SYSREF_DIV
R73 0 0 0 0 JESD_DAC2_CTRL JESD_DAC1_CTRL
R74 SYSREF_PULSE_CNT JESD_DAC4_CTRL JESD_DAC3_CTRL
R75 0 0 0 0 1 CHDIV 0 0 0 0 0 0
R76 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0
R77 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R78 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0
R79 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R81 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R82 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R83 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R84 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R86 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R88 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R89 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R90 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R91 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R92 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R93 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R94 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R95 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R96 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R97 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R98 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R99 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R100 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R101 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R102 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R103 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R104 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R105 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0
R106 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
R107 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R108 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1
R109 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R110 0 0 0 0 0 rb_LD
_VTUNE		 0 rb_VCO_SEL 0 0 0 0 0
R111 0 0 0 0 0 0 0 0 rb_VCO_CAPCTRL
R112 0 0 0 0 0 0 0 rb_VCO_DACISET
R113 rb_IO_STATUS
R114 0 0 0 0 0 0 WD_DLY WD_CNTRL

Table 20 lists the memory-mapped registers for the Device registers. All register offset addresses not listed in Table 20 should be considered as reserved locations and the register contents should not be modified.

Table 20. Device Registers

Offset Acronym Register Name Section
0x0 R0 Go
0x1 R1 Go
0x8 R8 Go
0x9 R9 Go
0xB R11 Go
0xC R12 Go
0xE R14 Go
0x10 R16 Go
0x13 R19 Go
0x14 R20 Go
0x1F R31 Go
0x22 R34 Go
0x24 R36 Go
0x25 R37 Go
0x26 R38 Go
0x27 R39 Go
0x28 R40 Go
0x29 R41 Go
0x2A R42 Go
0x2B R43 Go
0x2C R44 Go
0x2D R45 Go
0x2E R46 Go
0x3A R58 Go
0x3B R59 Go
0x3C R60 Go
0x45 R69 Go
0x46 R70 Go
0x47 R71 Go
0x48 R72 Go
0x49 R73 Go
0x4A R74 Go
0x4B R75 Go
0x6E R110 Go
0x6F R111 Go
0x70 R112 Go
0x71 R113 Go
0x72 R114 Go

Complex bit access types are encoded to fit into small table cells. Table 21 shows the codes that are used for access types in this section.

Table 21. Device Access Type Codes

Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value