SNAS730A March   2018  – November 2018 LMX8410L

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Configurations and Feature Description
        1. 7.3.1.1 RF, LO and IF Interfaces
          1. 7.3.1.1.1 RF Interface
          2. 7.3.1.1.2 LO Interface
            1. 7.3.1.1.2.1 LO Interface as Output Port
            2. 7.3.1.1.2.2 LO Interface as Input Port
          3. 7.3.1.1.3 Baseband Interface
        2. 7.3.1.2 Device Configurations Overview
          1. 7.3.1.2.1 Initialize the Device
          2. 7.3.1.2.2 Configure LO Modes
          3. 7.3.1.2.3 Set Up External LO Clock
          4. 7.3.1.2.4 Perform DCOC (DC Offset Correction)
          5. 7.3.1.2.5 Turn Off SM Clock
          6. 7.3.1.2.6 Perform IMRR (Image Rejection Ratio) Calibration
        3. 7.3.1.3 State Machine Clock
          1. 7.3.1.3.1 Set Divider Values For Internal LO Mode
          2. 7.3.1.3.2 Set Divider Values For External LO Mode
        4. 7.3.1.4 DCOC (DC Offset Correction)
          1. 7.3.1.4.1 RF Input Power Restriction During DCOC
          2. 7.3.1.4.2 Set Up DCOC Clock Divider
        5. 7.3.1.5 Image Rejection Calibration
          1. 7.3.1.5.1 Phase Calibration
          2. 7.3.1.5.2 Gain Calibration
        6. 7.3.1.6 IF Amplifier Common Mode Configurations
        7. 7.3.1.7 Synchronization Mode (Internal LO Mode Only)
          1. 7.3.1.7.1 Synchronization of the LO_OUT Output to the Fosc Input
          2. 7.3.1.7.2 Synchronization of I/Q Outputs to Fosc Inputs Using Internal LO
    4. 7.4 Device Functional Modes
      1. 7.4.1 Internal LO Mode
        1. 7.4.1.1 VCO Range Uncertainty for 7.5 to 7.7 GHz
      2. 7.4.2 External LO Mode
    5. 7.5 Programming
      1. 7.5.1 General Comments Regarding Programming
      2. 7.5.2 Recommended Initial Power Up Sequence
      3. 7.5.3 Recommended and Power on Reset Bit Values
    6. 7.6 Register Map
      1. 7.6.1  R0 Register (Address = 0x0) [reset = X]
        1. Table 9. R0 Register Field Descriptions
      2. 7.6.2  R1 Register (Address = 0x1) [reset = 0x3]
        1. Table 10. R1 Register Field Descriptions
      3. 7.6.3  R2 Register (Address = 0x2) [reset = X]
        1. Table 11. R2 Register Field Descriptions
      4. 7.6.4  R9 Register (Address = 0x9) [reset = X]
        1. Table 12. R9 Register Field Descriptions
      5. 7.6.5  R10 Register (Address = 0xA) [reset = 0x80]
        1. Table 13. R10 Register Field Descriptions
      6. 7.6.6  R11 Register (Address = 0xB) [reset = 0x10]
        1. Table 14. R11 Register Field Descriptions
      7. 7.6.7  R14 Register (Address = 0xE) [reset = 0x70]
        1. Table 15. R14 Register Field Descriptions
      8. 7.6.8  R36 Register (Address = 0x24) [reset = 0x64]
        1. Table 16. R36 Register Field Descriptions
      9. 7.6.9  R37 Register (Address = 0x25) [reset = 0x200]
        1. Table 17. R37 Register Field Descriptions
      10. 7.6.10 R38 Register (Address = 0x26) [reset = 0x0]
        1. Table 18. R38 Register Field Descriptions
      11. 7.6.11 R39 Register (Address = 0x27) [reset = 0x2710]
        1. Table 19. R39 Register Field Descriptions
      12. 7.6.12 R40 Register (Address = 0x28) [reset = 0x0]
        1. Table 20. R40 Register Field Descriptions
      13. 7.6.13 R41 Register (Address = 0x29) [reset = 0x0]
        1. Table 21. R41 Register Field Descriptions
      14. 7.6.14 R42 Register (Address = 0x2A) [reset = 0x0]
        1. Table 22. R42 Register Field Descriptions
      15. 7.6.15 R43 Register (Address = 0x2B) [reset = 0x0]
        1. Table 23. R43 Register Field Descriptions
      16. 7.6.16 R44 Register (Address = 0x2C) [reset = 0xA2]
        1. Table 24. R44 Register Field Descriptions
      17. 7.6.17 R46 Register (Address = 0x2E) [reset = 0x1]
        1. Table 25. R46 Register Field Descriptions
      18. 7.6.18 R58 Register (Address = 0x3A) [reset = 0x8000]
        1. Table 26. R58 Register Field Descriptions
      19. 7.6.19 R59 Register (Address = 0x3B) [reset = 0x1]
        1. Table 27. R59 Register Field Descriptions
      20. 7.6.20 R69 Register (Address = 0x45) [reset = 0x0]
        1. Table 28. R69 Register Field Descriptions
      21. 7.6.21 R70 Register (Address = 0x46) [reset = 0xC350]
        1. Table 29. R70 Register Field Descriptions
      22. 7.6.22 R75 Register (Address = 0x4B) [reset = 0x0]
        1. Table 30. R75 Register Field Descriptions
      23. 7.6.23 R78 Register (Address = 0x4E) [reset = 0x0]
        1. Table 31. R78 Register Field Descriptions
      24. 7.6.24 R79 Register (Address = 0x4F) [reset = 0x7000]
        1. Table 32. R79 Register Field Descriptions
      25. 7.6.25 R80 Register (Address = 0x50) [reset = 0xA]
        1. Table 33. R80 Register Field Descriptions
      26. 7.6.26 R81 Register (Address = 0x51) [reset = 0x0]
        1. Table 34. R81 Register Field Descriptions
      27. 7.6.27 R82 Register (Address = 0x52) [reset = 0x23]
        1. Table 35. R82 Register Field Descriptions
      28. 7.6.28 R83 Register (Address = 0x53) [reset = 0x2000]
        1. Table 36. R83 Register Field Descriptions
      29. 7.6.29 R84 Register (Address = 0x54) [reset = 0x1900]
        1. Table 37. R84 Register Field Descriptions
      30. 7.6.30 R88 Register (Address = 0x58) [reset = 0x0]
        1. Table 38. R88 Register Field Descriptions
      31. 7.6.31 R94 Register (Address = 0x5E) [reset = 0x8080]
        1. Table 39. R94 Register Field Descriptions
      32. 7.6.32 R95 Register (Address = 0x5F) [reset = X]
        1. Table 40. R95 Register Field Descriptions
      33. 7.6.33 R103 Register (Address = 0x67) [reset = X]
        1. Table 41. R103 Register Field Descriptions
      34. 7.6.34 R110 Register (Address = 0x6E) [reset = X]
        1. Table 42. R110 Register Field Descriptions
      35. 7.6.35 R111 Register (Address = 0x6F) [reset = 0x0]
        1. Table 43. R111 Register Field Descriptions
      36. 7.6.36 R112 Register (Address = 0x70) [reset = 0x0]
        1. Table 44. R112 Register Field Descriptions
      37. 7.6.37 R121 Register (Address = 0x79) [reset = 0x0]
        1. Table 45. R121 Register Field Descriptions
      38. 7.6.38 R123 Register (Address = 0x7B) [reset = 0x3]
        1. Table 46. R123 Register Field Descriptions
      39. 7.6.39 R126 Register (Address = 0x7E) [reset = X]
        1. Table 47. R126 Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 High Frequency Trace Routing
      2. 10.1.2 Power Trace Routing
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Measurements are done at 25 degree C. Parameters are measured at IF = 65MHz with high side injection, unless otherwise noted. Measurements are done with external VCM = 1.7V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
VCC Power supply voltage, 3.3-V rail 3.15 3.3 3.45 V
ICC Power supply current, 3.3-V rail Internal LO 650 mA
External LO 330
VCC5 Power supply voltage, 5-V rail 4.75 5 5.25 V
ICC5 Power supply current both channels I and Q, 5-V rail 130 mA
FREQUENCY RANGES
FRF RF port frequency range 4000 10000 MHz
FLO LO port frequency range 4000 10000 MHz
FIF IF port frequency range (3dB bandwidth) DC 1350 MHz
DYNAMIC PERFORMANCE
NF Noise figure RF = 4 GHz 15 dB
RF = 5 GHz 15
RF = 6 GHz 16
RF = 7 GHz 17
RF = 8 GHz 18
RF = 9 GHz 19
RF = 10 GHz 19
G Voltage gain(1) RF = 4 GHz 11 dB
RF = 5 GHz 11
RF = 6 GHz 10.5
RF = 7 GHz 9.5
RF = 8 GHz 9
RF = 9 GHz 8
RF = 10 GHz 7
IIP3 Input intercept point, 3rd order(2) RF = 4 GHz 28 dBm
RF = 5 GHz 28
RF = 6 GHz 26.5
RF = 7 GHz 27
RF = 8 GHz 26.5
RF = 9 GHz 27
RF = 10 GHz 27
IIP2 Input intercept point, 2nd order (uncalibrated) RF = 4 GHz 48 dBm
RF = 5 GHz 48
RF = 6 GHz 46
RF = 7 GHz 44
RF = 8 GHz 45
RF = 9 GHz 44
RF = 10 GHz 42
SP2x2 2×2 spur [RF input power at –10 dBm] RF = 4 GHz -58 dBc
RF = 5 GHz -58
RF = 6 GHz -58
RF = 7 GHz -54
RF = 8 GHz -52
RF = 9 GHz -50
RF = 10 GHz -48
SP3x3 3×3 spur [RF input power at –10 dBm] RF = 4 GHz -75 dBc
RF = 5 GHz -75
RF = 6 GHz -75
RF = 7 GHz -75
RF = 8 GHz -75
RF = 9 GHz -75
RF = 10 GHz -75
OP1dB Output 1-dB compression point RF = 4 GHz 12 dBm
RF = 5 GHz 12
RF = 6 GHz 12
RF = 7 GHz 12
RF = 8 GHz 12
RF = 9 GHz 12
RF = 10 GHz 12
IRR Image rejection ratio [calibrated] RF = 4 GHz 43 dB
RF = 5 GHz 43
RF = 6 GHz 44
RF = 7 GHz 44
RF = 8 GHz 43
RF = 9 GHz 42
RF = 10 GHz 36
ISORFxIF RF to IF isolation RF = 4 GHz 40 dB
RF = 5 GHz 40
RF = 6 GHz 40
RF = 7 GHz 40
RF = 8 GHz 40
RF = 9 GHz 40
RF = 10 GHz 40
LEAKRFxIF LO to IF leakage LO = 4 GHz -35 dBm
LO = 5 GHz -35
LO = 6 GHz -35
LO = 7 GHz -35
LO = 8 GHz -35
LO = 9 GHz -35
LO = 10 GHz -35
LEAKLOxRF LO to RF leakage (internal Lo mode) LO = 4 GHz -60 dBm
LO = 5 GHz -60
LO = 6 GHz -52
LO = 7 GHz -50
LO = 8 GHz -50
LO = 9 GHz -45
LO = 10 GHz –40
PERFORMANCE TUNING
GIQ_CAL I/Q gain calibration range IMRR_GCAL register full range ±0.5 dB
GIQ_STEP I/Q gain calibration step size 0.05 dB
PHIQ_CAL I/Q phase calibration range IMRR_PCAL register full range ±20 Deg
PHIQ_STEP I/Q phase calibration step size Step size can be made reduced to 0.25 deg in fine accuracy mode 0.45 Deg
VDCOC calibrated differential DC offset +/- 2 mV
PORTS
S11RF RF return loss RF = 4 GHz 8 dB
RF = 5 GHz 19 dB
RF = 6 GHz 21 dB
RF = 7 GHz 16 dB
RF = 8 GHz 10 dB
RF = 9 GHz 9 dB
RF = 10 GHz 9 dB
S11LO LO return loss (differential measurement) RF = 4 GHz 15 dB
RF = 5 GHz 15 dB
RF = 6 GHz 20 dB
RF = 7 GHz 17 dB
RF = 8 GHz 18 dB
RF = 9 GHz 17 dB
RF = 10 GHz 12 dB
PLO_IN External LO input power 8 GHz RFIN 6 dBm
PLO_OUT External LO output power(3) <7 GHz RFout 2 dBm
<10 GHz RFout -1 dBm
VIF_RANGE IF output voltage swing (differential) 2 VPP
VCM IF common mode voltage, internal or external source 1.2 1.7 2 V
PinRF RF input power 5 dBm
LO SYNTHESIZER INPUT SIGNAL PATH
FOSCIN Reference oscillator port frequency range OSC_2X = 0 5 1400 MHz
OSC_2X = 1 5 200
VOSCIN Reference input voltage AC-coupled required(4) 0.2 2 Vpp
FMULT Multiplier frequency (when multiplier enabled) Input range 30 70 MHz
Output range 180 250
LO SYNTHESIZER PHASE DETECTOR AND CHARGE PUMP
FPD Phase detector frequency Integer Mode (FRAC_ORDER = 0) 0.125 400 MHz
Fractional Mode (FRAC_ORDER = 1,2,3) 5 300
Fractional Mode (FRAC_ORDER = 4) 5 240
ICPOUT Charge pump leakage current CPG = 0 15 nA
Effective charge pump current (sum of up and down currents) CPG = 4 3 mA
CPG = 1 6
CPG = 5 9
CPG = 3 12
CPG = 7 15
PN1/F Normalized PLL flicker noise FPD = 100 MHz, FVCO = 12 GHz(5) –129 dBc/Hz
PNFLAT Normalized PLL thermal noise floor –236 dBc/Hz
LO SYNTHESIZER VCO
PNvco Open loop VCO phase noise 8 GHz VCO, 10 kHz offset –80 dBc/Hz
8 GHz VCO, 100 kHz offset –107
8 GHz VCO, 1 MHz offset –128
8 GHz VCO, 10 MHz offset –148
8 GHz VCO, 90 MHz offset –157
9.2 GHz VCO, 10 kHz offset –79
9.2 GHz VCO, 100 kHz offset –105
9.2 GHz VCO, 1 MHz offset –127
9.2 GHz VCO, 10 MHz offset –147
9.2 GHz VCO, 90 MHz offset –157
10.3 GHz VCO, 10 kHz offset –77
10.3 GHz VCO, 100 kHz offset –104
10.3 GHz VCO, 1 MHz offset –126
10.3 GHz VCO, 10 MHz offset –147
10.3 GHz VCO, 90 MHz offset –157
11.3 GHz VCO, 10 kHz offset –76
11.3 GHz VCO, 100 kHz offset –103
11.3 GHz VCO, 1 MHz offset –125
11.3 GHz VCO, 10 MHz offset –145
11.3 GHz VCO, 90 MHz offset –158
12.5 GHz VCO, 10 kHz offset –74
12.5 GHz VCO, 100 kHz offset –100
12.5 GHz VCO, 1 MHz offset –123
12.5 GHz VCO, 10 MHz offset –144
12.5 GHz VCO, 90 MHz offset –157
13.3 GHz VCO, 10 kHz offset –73
13.3 GHz VCO, 100 kHz offset –100
13.3 GHz VCO, 1 MHz offset –122
13.3 GHz VCO, 10 MHz offset –143
13.3 GHz VCO, 90 MHz offset –155
14.5 GHz VCO, 10 kHz offset –73
14.5 GHz VCO, 100 kHz offset –99
14.5 GHz VCO, 1 MHz offset –121
14.5 GHz VCO, 10 MHz offset –143
14.5 GHz VCO, 90 MHz offset –152
tVCO_CAL VCO calibration speed, switch across the entire frequency band, FOSC = 200 MHz, FPD = 100 MHz(6) No assist 50 µs
Close frequency 20
KVCO VCO gain 8 GHz 89 MHz/V
9.2 GHz 93
10.3 GHz 110
11.3 GHz 124
12.5 GHz 189
13.3 GHz 182
14.5 GHz 205
|ΔTCL| Allowable temperature drift when VCO is not re-calibrated 125 °C
H2 VCO second harmonic FVCO = 8 GHz, divider disabled -30 dBc
H3 VCO third harmonic FVCO = 8 GHz, divider disabled -40
SYNC PIN AND PHASE ALIGNMENT
FOSCIN_SYNC Maximum usable OSCIN frequency with SYNC pin Category 3 (int LO mode) 0 100 MHz
Category 1 or 2 0 1400
DIGITAL INTERFACE (SCK, SDI, CSB, MUXOUT, SYNC, CE)
VIH High level input voltage 1.4 VCC V
VIL Low level input voltage 0 0.4 V
IIH High level input current -50 50 µA
IIL Low level input current -50 50 µA
VOH High level output voltage IL = –5 mA VCC – 0.55 V
VOL High level output current IL = 5 mA 0.55 V
(1) For measurements that require RF input, RF input power is -10dBm unless otherwise specified.
(2) For two-tone measurements, tone separation is 17MHz.
(3) Output power, spurs, and harmonics can vary based on board layout and components.
(4) For lower VCO frequencies, the N divider minimum value can limit the phase detector frequency.
(5) The PLL noise contribution is measured using a clean reference and a wide loop bandwidth and is composed into flicker and flat components. PLLFLAT = PLLFOM + 20log(FVCO / FPD) + 10log(FPD / 1Hz). PLLFLICKER (offset) = PLLFLICKER_NORM + 20log(FVCO / 1GHz) - 10log(offset frequency / 10kHz). Once these two components are found, the total PLL noise can be calculated as PLLNOISE = 10log(10PLLFLAT / 10 + 10PLLFLICKER / 10).
(6) See Application and Implementation for more details on the different VCO calibration modes.