SNVS171J November 2001 – January 2017 LP2992
The LP2992 family of fixed-output, ultralow-dropout, and low-noise regulators offer exceptional and cost-effective performance for battery-powered applications. Available in output voltages from 1.5 V to 5 V, the family has an output tolerance of 1% for the A version and is capable of delivering 250-mA continuous load current. Using an optimized vertically integrated PNP (VIP) process, the LP2992 delivers unequaled performance. The dropout voltage and the GND pin current with 250 mA of load current are typically 450 mV and 1500 µA, respectively.
When the ON/OFF pin is pulled low, the LP2992 enters a sleep mode, and less than 1-µA quiescent current is consumed. This function is designed for the application which needs a sleep mode to effectively enhance battery life cycle.
The LP2992 uses a vertical PNP process which allows for quiescent currents which are considerably lower than those associated with traditional lateral PNP regulators, typically 1500 µA at 250-mA load and 75 µA at 1-mA load.
The LP2992 includes a low-noise reference ensuring minimal noise during operation because the internal reference is normally the dominant term in a noise analysis. Further noise reduction can be achieved by adding an external bypass capacitor between the BYPASS pin and the GND pin. For more detailed information on noise reduction using the BYPASS pin, see Noise Bypass Capacitor.
The LP2992 is designed specifically to work with ceramic output capacitors using circuitry that allows the regulator to be stable across the entire range of output current with an output capacitor whose ESR is as low as 5 mΩ. For output capacitor requirements, see Output Capacitor.
The internal current-limit circuit is used to protect the LDO against high-current faults or shorting events. The LDO is not designed to operate in a steady-state current limit. During a current-limit event, the LDO sources constant current. Therefore, the output voltage falls when the output impedance decreases. Note also that if a current limit occurs and the resulting output voltage is low, excessive power may be dissipated across the LDO, resulting in a thermal shutdown of the output.
The LP2992 is featured with the foldback current limit that allows a high peak current when VOUT > 0.5 V, and then reduces the maximum output current as VOUT is forced to ground.
The LP2992 is designed with the thermal shutdown circuitry to turn off the output when excessive heat is dissipated in the LDO. The internal protection circuitry of the LP2992 is designed to protect against thermal overload conditions. Continuously running the device into thermal shutdown degrades its reliability.
The LP2992 operates if the input voltage is equal to or exceeds VOUT(TARGET) + 0.9 V. At input voltages below the minimum VIN requirement, the device does not operate correctly and output voltage may not reach a target value.
If the voltage on the ON/OFF pin is less than 0.15 V, the device is disabled and, in this shutdown state, current does not exceed 2 µA. Raising the voltage at the ON/OFF pin above 1.6 V initiates the start-up sequence of the device. If this feature is not to be used, the ON/OFF input must be tied to VIN to keep the regulator output on at all times.
To assure proper operation, the signal source used to drive the ON/OFF input must be able to swing above and below the specified turnon/turnoff voltage thresholds listed in the Electrical Characteristics section under VON/OFF. To prevent mis-operation, the turnon (and turnoff) voltage signals applied to the ON/OFF input must have a slew rate which is ≥ 40 mV/µs.
The regulator output voltage can not be ensured if a slow-moving AC (or DC) signal is applied that is in the range between the specified turnon and turnoff voltages listed under the electrical specification VON/OFF (see Electrical Characteristics).