SNVSC57 September   2022 LP5912-EP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Output and Input Capacitors
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable (EN)
      2. 7.3.2 Output Automatic Discharge (RAD)
      3. 7.3.3 Reverse Current Protection (IRO)
      4. 7.3.4 Internal Current Limit (ISC)
      5. 7.3.5 Thermal Overload Protection (TSD)
      6. 7.3.6 Power-Good Output (PG)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable (EN)
      2. 7.4.2 Minimum Operating Input Voltage (VIN)
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Capacitors
        2. 8.2.2.2 Input Capacitor
        3. 8.2.2.3 Output Capacitor
        4. 8.2.2.4 Capacitor Characteristics
        5. 8.2.2.5 Remote Capacitor Operation
        6. 8.2.2.6 Power Dissipation
        7. 8.2.2.7 Estimating Junction Temperature
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
  10. 10Electrostatic Discharge Caution
  11. 11Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.7 Estimating Junction Temperature

The EIA/JEDEC standard recommends the use of psi (Ψ) thermal characteristics to estimate the junction temperatures of surface-mount devices on a typical PCB board application. These characteristics are not true thermal resistance values, but rather package-specific thermal characteristics that offer practical and relative means of estimating junction temperatures. These psi metrics are determined to be significantly independent of copper-spreading area. The key thermal characteristics (ΨJT and ΨJB) are used in accordance with Equation 4 or Equation 5 and are given in the Section 6.4 table.

Equation 4. TJ(MAX) = TTOP + (ΨJT × PD(MAX))

where:

  • PD(MAX) is explained in Equation 3
  • TTOP is the temperature measured at the center-top of the device package
Equation 5. TJ(MAX) = TBOARD + (ΨJB × PD(MAX))

where:

  • PD(MAX) is explained in the Section 8.2.2.6 section
  • TBOARD is the PCB surface temperature measured 1 mm from the device package and centered on the package edge

For more information about the thermal characteristics ΨJT and ΨJB, see the Semiconductor and IC Package Thermal Metrics application note; for more information about measuring TTOP and TBOARD, see the Using New Thermal Metrics application note; and for more information about the EIA/JEDEC JESD51 PCB used for validating RθJA, see the Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs application note. These application notes are available at www.ti.com.