SNVSAT4A September   2017  – June 2021 LP873220-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Serial Bus Timing Parameters
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DC/DC Converters
        1. 7.3.1.1 Overview
        2. 7.3.1.2 Transition Between PWM and PFM Modes
        3. 7.3.1.3 Buck Converter Load Current Measurement
        4. 7.3.1.4 Spread-Spectrum Mode
      2. 7.3.2  Sync Clock Functionality
      3. 7.3.3  Low-Dropout Linear Regulators (LDOs)
      4. 7.3.4  Power-Up
      5. 7.3.5  Regulator Control
        1. 7.3.5.1 Enabling and Disabling Regulators
        2. 7.3.5.2 Changing Output Voltage
      6. 7.3.6  Enable and Disable Sequences
      7. 7.3.7  Device Reset Scenarios
      8. 7.3.8  Diagnosis and Protection Features
        1. 7.3.8.1 Power-Good Information (PGOOD pin)
          1. 7.3.8.1.1 PGOOD Pin Gated Mode
          2. 7.3.8.1.2 PGOOD Pin Continuous Mode
          3. 7.3.8.1.3 PGOOD Pin Inactive Mode
        2. 7.3.8.2 Warnings for Diagnosis (Interrupt)
          1. 7.3.8.2.1 Output Power Limit
          2. 7.3.8.2.2 Thermal Warning
        3. 7.3.8.3 Protection (Regulator Disable)
          1. 7.3.8.3.1 Short-Circuit and Overload Protection
          2. 7.3.8.3.2 Overvoltage Protection
          3. 7.3.8.3.3 Thermal Shutdown
        4. 7.3.8.4 Fault (Power Down)
          1. 7.3.8.4.1 Undervoltage Lockout
      9. 7.3.9  Operation of the GPO Signals
      10. 7.3.10 Digital Signal Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start and Stop Conditions
        3. 7.5.1.3 Transferring Data
        4. 7.5.1.4 I2C-Compatible Chip Address
        5. 7.5.1.5 Auto-Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1. 7.6.1.1  DEV_REV
        2. 7.6.1.2  OTP_REV
        3. 7.6.1.3  BUCK0_CTRL_1
        4. 7.6.1.4  BUCK0_CTRL_2
        5. 7.6.1.5  BUCK1_CTRL_1
        6. 7.6.1.6  BUCK1_CTRL_2
        7. 7.6.1.7  BUCK0_VOUT
        8. 7.6.1.8  BUCK1_VOUT
        9. 7.6.1.9  LDO0_CTRL
        10. 7.6.1.10 LDO1_CTRL
        11. 7.6.1.11 LDO0_VOUT
        12. 7.6.1.12 LDO1_VOUT
        13. 7.6.1.13 BUCK0_DELAY
        14. 7.6.1.14 BUCK1_DELAY
        15. 7.6.1.15 LDO0_DELAY
        16. 7.6.1.16 LDO1_DELAY
        17. 7.6.1.17 GPO_DELAY
        18. 7.6.1.18 GPO2_DELAY
        19. 7.6.1.19 GPO_CTRL
        20. 7.6.1.20 CONFIG
        21. 7.6.1.21 PLL_CTRL
        22. 7.6.1.22 PGOOD_CTRL_1
        23. 7.6.1.23 PGOOD_CTRL_2
        24. 7.6.1.24 PG_FAULT
        25. 7.6.1.25 RESET
        26. 7.6.1.26 INT_TOP_1
        27. 7.6.1.27 INT_TOP_2
        28. 7.6.1.28 INT_BUCK
        29. 7.6.1.29 INT_LDO
        30. 7.6.1.30 TOP_STAT
        31. 7.6.1.31 BUCK_STAT
        32. 7.6.1.32 LDO_STAT
        33. 7.6.1.33 TOP_MASK_1
        34. 7.6.1.34 TOP_MASK_2
        35. 7.6.1.35 BUCK_MASK
        36. 7.6.1.36 LDO_MASK
        37. 7.6.1.37 SEL_I_LOAD
        38. 7.6.1.38 I_LOAD_2
        39. 7.6.1.39 I_LOAD_1
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Inductor Selection
        2. 8.2.1.2 Buck Input Capacitor Selection
        3. 8.2.1.3 Buck Output Capacitor Selection
        4. 8.2.1.4 LDO Input Capacitor Selection
        5. 8.2.1.5 LDO Output Capacitor Selection
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6.1 Register Descriptions

The LP873220-Q1 is controlled by a set of registers through the I2C-compatible interface. The device registers addresses and abbreviations are listed in Table 7-7. A more detailed description is given in the Section 7.6.1.1 to Section 7.6.1.39 sections.

The asterisk (*) marking indicates register bits which are updated from OTP memory during READ OTP state.

Note:

This register map describes the default values for a device with orderable code of LP873220RHDRQ1. For other device versions the default values read from OTP memory can be different.

Table 7-7 Summary of LP873220-Q1 Control Registers
AddrRegisterRead / WriteD7D6D5D4D3D2D1D0
0x00DEV_REVRDEVICE_ID[1:0]Reserved - do not use
0x01OTP_REVROTP_ID[7:0]
0x02BUCK0_
CTRL_1		R/WReserved - do not useBUCK0_FPWMBUCK0_RDIS_ENBUCK0_
EN_PIN_CTRL		BUCK0_EN
0x03BUCK0_
CTRL_2		R/WReserved - do not useBUCK0_ILIM[2:0]BUCK0_SLEW_RATE[2:0]
0x04BUCK1_
CTRL_1		R/WReserved - do not useBUCK1_FPWMBUCK1_RDIS_ENBUCK1_
EN_PIN_CTRL		BUCK1_EN
0x05BUCK1_
CTRL_2		R/WReserved - do not useBUCK1_ILIM[2:0]BUCK1_SLEW_RATE[2:0]
0x06BUCK0_
VOUT		R/WBUCK0_VSET[7:0]
0x07BUCK1_
VOUT		R/WBUCK1_VSET[7:0]
0x08LDO0_
CTRL		R/WReserved - do not useLDO0_RDIS_ENLDO0_
EN_PIN_CTRL		LDO0_EN
0x09LDO1_
CTRL		R/WReserved - do not useLDO1_RDIS_ENLDO1_
EN_PIN_CTRL		LDO1_EN
0x0ALDO0_
VOUT		R/WReserved - do not useLDO0_VSET[4:0]
0x0BLDO1_
VOUT		R/WReserved - do not useLDO1_VSET[4:0]
0x0CBUCK0_
DELAY		R/WBUCK0_SHUTDOWN_DELAY[3:0]BUCK0_STARTUP_DELAY[3:0]
0x0DBUCK1_
DELAY		R/WBUCK1_SHUTDOWN_DELAY[3:0]BUCK1_STARTUP_DELAY[3:0]
0x0ELDO0_
DELAY		R/WLDO0_SHUTDOWN_DELAY[3:0]LDO0_STARTUP_DELAY[3:0]
0x0FLDO1_
DELAY		R/WLDO1_SHUTDOWN_DELAY[3:0]LDO1_STARTUP_DELAY[3:0]
0x10GPO_
DELAY		R/WGPO_SHUTDOWN_DELAY[3:0]GPO_STARTUP_DELAY[3:0]
0x11GPO2_
DELAY		R/WGPO2_SHUTDOWN_DELAY[3:0]GPO2_STARTUP_DELAY[3:0]
0x12GPO_
CTRL		R/WReserved - do not useGPO2_ODGPO2_
EN_PIN_CTRL		GPO2_ENReserved - do not useGPO_ODGPO_
EN_PIN_CTRL		GPO_EN
0x13CONFIGR/WReserved - do not useSTARTUP_DELAY_SELSHUTDOWN_DELAY_SELCLKIN_PIN_SELCLKIN_PDEN_PDTDIE
_WARN
_LEVEL		EN_
SPREAD
_SPEC
0x14PLL_CTRLR/WReserved - do not useEN_PLLReserved - do not useEXT_CLK_FREQ[4:0]
0x15PGOOD_CTRL_1R/WPGOOD_POLPGOOD_ODPGOOD_WINDOW_LDOPGOOD_WINDOW_BUCKEN_PGOOD_LDO1EN_PGOOD_LDO0EN_PGOOD_BUCK1EN_PGOOD_BUCK0
0x16PGOOD_CTRL_2R/WReserved - do not useEN_PGOOD_TWARNPG_FAULT_GATES_PGOODPGOOD_MODE
0x17PG_FAULTRReserved - do not usePG_FAULT_LDO1PG_FAULT_LDO0PG_FAULT_BUCK1PG_FAULT_BUCK0
0x18RESETR/WReserved - do not useSW_
RESET
0x19INT_TOP_1R/WPGOOD_
INT		INT_
LDO		INT_
BUCK		SYNC_
CLK_INT		TDIE_SD_INTTDIE_
WARN_INT		OVP_INTI_MEAS_
INT
0x1AINT_TOP_2R/WReserved - do not useRESET_
REG_INT
0x1BINT_BUCKR/WReserved - do not useBUCK1_
PG_INT		BUCK1_
SC_INT		BUCK1_
ILIM_INT		Reserved - do not useBUCK0_
PG_INT		BUCK0_
SC_INT		BUCK0_
ILIM_INT
0x1CINT_LDOR/WReserved - do not useLDO1_
PG_INT		LDO1_
SC_INT		LDO1_
ILIM_INT		Reserved - do not useLDO0_
PG_INT		LDO0_
SC_INT		LDO0_
ILIM_INT
0x1DTOP_
STAT		RPGOOD_STATReserved - do not useSYNC_CLK
_STAT		TDIE_SD
_STAT		TDIE_
WARN_
STAT		OVP_
STAT		Reserved - do not use
0x1EBUCK_STATRBUCK1_
STAT		BUCK1_
PG_STAT		Reserved - do not useBUCK1_
ILIM_STAT		BUCK0_
STAT		BUCK0_
PG_STAT		Reserved - do not useBUCK0_
ILIM_STAT
0x1FLDO_STATRLDO1_
STAT		LDO1_
PG_STAT		Reserved - do not useLDO1_
ILIM_STAT		LDO0_
STAT		LDO0_
PG_STAT		Reserved - do not useLDO0_
ILIM_STAT
0x20TOP_
MASK_1		R/WPGOOD_
INT_MASK		Reserved - do not useSYNC_CLK
_MASK		Reserved - do not useTDIE_WARN_MASKReserved - do not useI_MEAS_
MASK
0x21TOP_
MASK_2		R/WReserved - do not useRESET_
REG_MASK
0x22BUCK_MASKR/WBUCK1_PGF_MASKBUCK1_PGR_MASKReserved - do not useBUCK1_
ILIM_
MASK		BUCK0_PGF_MASKBUCK0_PGR_MASKReserved - do not useBUCK0_
ILIM_
MASK
0x23LDO_MASKR/WLDO1_PGF_MASKLDO1_PGR_MASKReserved - do not useLDO1_
ILIM_
MASK		LDO0_PGF_MASKLDO0_PGR_MASKReserved - do not useLDO0_
ILIM_
MASK
0x24SEL_I_
LOAD		R/WReserved - do not useLOAD_CURRENT_
BUCK_SELECT
0x25I_LOAD_2RReserved - do not useBUCK_LOAD_CURRENT[8]
0x26I_LOAD_1RBUCK_LOAD_CURRENT[7:0]