SNVSAT4A September 2017 – June 2021 LP873220-Q1
INT_TOP_2 is shown in Table 7-61, Address: 0x1A
|Reserved - do not use||RESET_REG_INT|
|7:1||Reserved - do not use||R/W||000 0000|
|0||RESET_REG_INT||R/W||0||Latched status bit indicating that either VANA supply voltage has been below the undervoltage threshold level or the host has requested a reset using the SW_RESET bit in RESET register. The regulators have been disabled, the registers are reset to the default values, and the normal startup procedure is done.|
Write 1 to clear interrupt.