SNVSAT4A September 2017 – June 2021 LP873220-Q1
The LP873220-Q1 is controlled through an I2C-compatible interface. START and STOP conditions classify the beginning and end of the I2C session. A START condition is defined as SDA transitions from HIGH to LOW while SCL is HIGH. A STOP condition is defined as an SDA transition from LOW to HIGH while SCL is HIGH. The I2C master always generates the START and STOP conditions.
The I2C bus is considered busy after a START condition and free after a STOP condition. During data transmission, the I2C master can generate repeated START conditions. A START and a repeated START condition are equivalent function-wise. The data on SDA must be stable during the HIGH period of the clock signal (SCL). In other words, the state of SDA can only be changed when SCL is LOW. Figure 7-16 shows the SDA and SCL signal timing for the I2C-compatible bus. See Section 6.6 for the timing values.