SNVSBK2 September   2019 LP8733

PRODUCTION DATA.  

  1. Features
    1.     Simplified Schematic
  2. Applications
  3. Description
    1.     DC/DC Efficiency vs Output Current
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Serial Bus Timing Parameters
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DC/DC Converters
        1. 7.3.1.1 Overview
        2. 7.3.1.2 Dual-Phase Operation and Phase-Adding/Shedding
        3. 7.3.1.3 Transition Between PWM and PFM Modes
        4. 7.3.1.4 Dual-Phase Switcher Configurations
        5. 7.3.1.5 Buck Converter Load Current Measurement
        6. 7.3.1.6 Spread-Spectrum Mode
      2. 7.3.2  Sync Clock Functionality
      3. 7.3.3  Low-Dropout Linear Regulators (LDOs)
      4. 7.3.4  Power-Up
      5. 7.3.5  Regulator Control
        1. 7.3.5.1 Enabling and Disabling Regulators
        2. 7.3.5.2 Changing Output Voltage
      6. 7.3.6  Enable and Disable Sequences
      7. 7.3.7  Device Reset Scenarios
      8. 7.3.8  Diagnosis and Protection Features
        1. 7.3.8.1 Power-Good Information (PGOOD pin)
          1. 7.3.8.1.1 PGOOD Pin Gated Mode
          2. 7.3.8.1.2 PGOOD Pin Continuous Mode
        2. 7.3.8.2 Warnings for Diagnosis (Interrupt)
          1. 7.3.8.2.1 Output Power Limit
          2. 7.3.8.2.2 Thermal Warning
        3. 7.3.8.3 Protection (Regulator Disable)
          1. 7.3.8.3.1 Short-Circuit and Overload Protection
          2. 7.3.8.3.2 Overvoltage Protection
          3. 7.3.8.3.3 Thermal Shutdown
        4. 7.3.8.4 Fault (Power Down)
          1. 7.3.8.4.1 Undervoltage Lockout
      9. 7.3.9  Operation of the GPO Signals
      10. 7.3.10 Digital Signal Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start and Stop Conditions
        3. 7.5.1.3 Transferring Data
        4. 7.5.1.4 I2C-Compatible Chip Address
        5. 7.5.1.5 Auto-Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1. 7.6.1.1  DEV_REV
          1. Table 8. DEV_REV Register Field Descriptions
        2. 7.6.1.2  OTP_REV
          1. Table 9. OTP_REV Register Field Descriptions
        3. 7.6.1.3  BUCK0_CTRL_1
          1. Table 10. BUCK0_CTRL_1 Register Field Descriptions
        4. 7.6.1.4  BUCK0_CTRL_2
          1. Table 11. BUCK0_CTRL_2 Register Field Descriptions
        5. 7.6.1.5  BUCK1_CTRL_1
          1. Table 12. BUCK1_CTRL_1 Register Field Descriptions
        6. 7.6.1.6  BUCK1_CTRL_2
          1. Table 13. BUCK1_CTRL_2 Register Field Descriptions
        7. 7.6.1.7  BUCK0_VOUT
          1. Table 14. BUCK0_VOUT Register Field Descriptions
        8. 7.6.1.8  BUCK1_VOUT
          1. Table 15. BUCK1_VOUT Register Field Descriptions
        9. 7.6.1.9  LDO0_CTRL
          1. Table 16. LDO0_CTRL Register Field Descriptions
        10. 7.6.1.10 LDO1_CTRL
          1. Table 17. LDO1_CTRL Register Field Descriptions
        11. 7.6.1.11 LDO0_VOUT
          1. Table 18. LDO0_VOUT Register Field Descriptions
        12. 7.6.1.12 LDO1_VOUT
          1. Table 19. LDO1_VOUT Register Field Descriptions
        13. 7.6.1.13 BUCK0_DELAY
          1. Table 20. BUCK0_DELAY Register Field Descriptions
        14. 7.6.1.14 BUCK1_DELAY
          1. Table 21. BUCK1_DELAY Register Field Descriptions
        15. 7.6.1.15 LDO0_DELAY
          1. Table 22. LDO0_DELAY Register Field Descriptions
        16. 7.6.1.16 LDO1_DELAY
          1. Table 23. LDO1_DELAY Register Field Descriptions
        17. 7.6.1.17 GPO_DELAY
          1. Table 24. GPO_DELAY Register Field Descriptions
        18. 7.6.1.18 GPO2_DELAY
          1. Table 25. GPO2_DELAY Register Field Descriptions
        19. 7.6.1.19 GPO_CTRL
          1. Table 26. GPO_CTRL Register Field Descriptions
        20. 7.6.1.20 CONFIG
          1. Table 27. CONFIG Register Field Descriptions
        21. 7.6.1.21 PLL_CTRL
          1. Table 28. PLL_CTRL Register Field Descriptions
        22. 7.6.1.22 PGOOD_CTRL_1
          1. Table 29. PGOOD_CTRL_1 Register Field Descriptions
        23. 7.6.1.23 PGOOD_CTRL_2
          1. Table 30. PGOOD_CTRL_2 Register Field Descriptions
        24. 7.6.1.24 PG_FAULT
          1. Table 31. PG_FAULT Register Field Descriptions
        25. 7.6.1.25 RESET
          1. Table 32. RESET Register Field Descriptions
        26. 7.6.1.26 INT_TOP_1
          1. Table 33. INT_TOP_1 Register Field Descriptions
        27. 7.6.1.27 INT_TOP_2
          1. Table 34. INT_TOP_2 Register Field Descriptions
        28. 7.6.1.28 INT_BUCK
          1. Table 35. INT_BUCK Register Field Descriptions
        29. 7.6.1.29 INT_LDO
          1. Table 36. INT_LDO Register Field Descriptions
        30. 7.6.1.30 TOP_STAT
          1. Table 37. TOP_STAT Register Field Descriptions
        31. 7.6.1.31 BUCK_STAT
          1. Table 38. BUCK_STAT Register Field Descriptions
        32. 7.6.1.32 LDO_STAT
          1. Table 39. LDO_STAT Register Field Descriptions
        33. 7.6.1.33 TOP_MASK_1
          1. Table 40. TOP_MASK_1 Register Field Descriptions
        34. 7.6.1.34 TOP_MASK_2
          1. Table 41. TOP_MASK_2 Register Field Descriptions
        35. 7.6.1.35 BUCK_MASK
          1. Table 42. BUCK_MASK Register Field Descriptions
        36. 7.6.1.36 LDO_MASK
          1. Table 43. LDO_MASK Register Field Descriptions
        37. 7.6.1.37 SEL_I_LOAD
          1. Table 44. SEL_I_LOAD Register Field Descriptions
        38. 7.6.1.38 I_LOAD_2
          1. Table 45. I_LOAD_2 Register Field Descriptions
        39. 7.6.1.39 I_LOAD_1
          1. Table 46. I_LOAD_1 Register Field Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Inductor Selection
        2. 8.2.1.2 Buck Input Capacitor Selection
        3. 8.2.1.3 Buck Output Capacitor Selection
        4. 8.2.1.4 LDO Input Capacitor Selection
        5. 8.2.1.5 LDO Output Capacitor Selection
        6. 8.2.1.6 Current Limit vs. Maximum Output Current
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Enabling and Disabling Regulators

The regulators can be enabled when the device is in STANDBY or ACTIVE state. There are two ways to enable and disable the buck regulators:

  • Using the BUCKx_EN bit in the BUCKx_CTRL_1 register (the BUCKx_EN_PIN_CTRL bit is 0 in the BUCKx_CTRL_1 register).
  • Using the EN control pin (the BUCKx_EN bit and the BUCKx_EN_PIN_CTRL bit is 1).

Similarly, there are two ways to enable and disable the LDO regulators:

  • Using the LDOx_EN bit in the LDOx_CTRL register (the LDOx_EN_PIN_CTRL bit is 0 in the LDOx_CTRL register).
  • Using the EN control pin (the LDOx_EN bit is 1 and the LDOx_EN_PIN_CTRL bit is 1).

If the EN control pin is used for enable and disable, then the following occurs:

  • The delay from the control signal rising edge to start-up is set by the BUCKx_STARTUP_DELAY[3:0] bits in the BUCKx_DELAY register and the LDOx_STARTUP_DELAY[3:0] bits in the LDOx_DELAY register.
  • The delay from the control signal falling edge to shutdown is set by the BUCKx_SHUTDOWN_DELAY[3:0] bits in the BUCKx_DELAY register and the LDOx_SHUTDOWN_DELAY[3:0] bits in the LDOx_DELAY register.
The delays are only valid for the EN signal transitions and not for control with I2C writings to the BUCKx_EN and the LDOx_EN bits.

The control of the regulator (with 0-ms delays) is shown in Table 3. Dual-phase regulator is controlled with registers of the master phase.

Table 3. Regulator Control

BUCKx_EN AND
LDOx_EN
BUCKx_EN_PIN_CTRL AND
LDOx_EN_PIN_CTRL
EN PIN BUCKx OUTPUT VOLTAGE AND
LDOx OUTPUT VOLTAGE
Enable and disable control with the BUCKx_EN and the LDOx_EN bit 0 Don't Care Don't Care Disabled
1 0 Don't Care BUCKx_VSET[7:0] and LDOx_VSET[4:0]
Enable and disable control with the EN pin 1 1 Low Disabled
1 1 High BUCKx_VSET[7:0] and LDOx_VSET[4:0]

The buck regulator is enabled by the EN pin or by I2C writing, as shown in Figure 13. The soft-start circuit limits the in-rush current during start-up. When the output voltage rises to a 0.35-V level, the output voltage becomes slew-rate controlled. If there is a short circuit at the output, and the output voltage does not increase above the 0.35-V level in 1 ms or the output voltage drops below 0.35-V level during operation (for minimum of 1 ms), then the regulator is disabled, and the BUCKx_SC_INT interrupt in the INT_BUCK register is set. When the output voltage reaches the the Power-Good threshold level, the BUCKx_PG_INT interrupt flag in the INT_BUCK register is set. The Power-Good interrupt flag, when reaching the valid output voltage, can be masked using the BUCKx_PGR_MASK bit in the BUCK_MASK register. The Power-Good interrupt flag can also be generated when the output voltage becomes invalid. The interrupt mask for invalid output voltage detection is set by the BUCKx_PGF_MASK bit in the BUCK_MASK register. A BUCKx_PG_STAT bit in the BUCK_STAT register always shows the validity of the output voltage; 1 means valid and 0 means invalid output voltage. A PGOOD_WINDOW_BUCK bit in the PGOOD_CTRL_1 register sets the detection method for the valid buck output voltage, either under-voltage detection, or under-voltage and over-voltage detection.

LP8733 Enable_Disable_Buck.gifFigure 13. Buck Regulator Enable and Disable

The LDO regulator is enabled by the EN pin or by I2C writing, as shown in Figure 14. The soft-start circuit limits the in-rush current during start-up. The output voltage increase rate is less than 100 mV/μsec during soft-start. If there is a short circuit at the output, and the output voltage does not increase above the 0.3-V level in 1 ms or the output voltage drops below 0.3-V level during operation (for minimum of 1 ms), then the regulator is disabled, and the LDOx_SC_INT interrupt in the INT_LDO register is set. When the output voltage reaches the Power-Good threshold level, the LDOx_PG_INT interrupt flag in the INT_LDO register is set. The Power-Good interrupt flag, when reaching valid output voltage, can be masked using the LDOx_PGR_MASK bit in the LDO_MASK register. The Power-Good interrupt flag can also be generated when the output voltage becomes invalid. The interrupt mask for invalid output voltage detection is set by the LDOx_PGF_MASK bit in the LDO_MASK register. A LDOx_PG_STAT bit in the LDO_STAT register always shows the validity of the output voltage; 1 means valid, and 0 means invalid output voltage. A PGOOD_WINDOW_LDO bit in the PGOOD_CTRL_1 register sets the detection method for the valid LDO output voltage, either undervoltage detection or undervoltage and overvoltage detection.

LP8733 Enable_Disable_LDO.gifFigure 14. LDO Regulator Enable and Disable

The EN input pin has an integrated pulldown resistor. The pulldown resistor is controlled with the EN_PD bit in the CONFIG register.