SNVSBK2 September   2019 LP8733


  1. Features
    1.     Simplified Schematic
  2. Applications
  3. Description
    1.     DC/DC Efficiency vs Output Current
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Serial Bus Timing Parameters
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DC/DC Converters
        1. Overview
        2. Dual-Phase Operation and Phase-Adding/Shedding
        3. Transition Between PWM and PFM Modes
        4. Dual-Phase Switcher Configurations
        5. Buck Converter Load Current Measurement
        6. Spread-Spectrum Mode
      2. 7.3.2  Sync Clock Functionality
      3. 7.3.3  Low-Dropout Linear Regulators (LDOs)
      4. 7.3.4  Power-Up
      5. 7.3.5  Regulator Control
        1. Enabling and Disabling Regulators
        2. Changing Output Voltage
      6. 7.3.6  Enable and Disable Sequences
      7. 7.3.7  Device Reset Scenarios
      8. 7.3.8  Diagnosis and Protection Features
        1. Power-Good Information (PGOOD pin)
          1. PGOOD Pin Gated Mode
          2. PGOOD Pin Continuous Mode
        2. Warnings for Diagnosis (Interrupt)
          1. Output Power Limit
          2. Thermal Warning
        3. Protection (Regulator Disable)
          1. Short-Circuit and Overload Protection
          2. Overvoltage Protection
          3. Thermal Shutdown
        4. Fault (Power Down)
          1. Undervoltage Lockout
      9. 7.3.9  Operation of the GPO Signals
      10. 7.3.10 Digital Signal Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. Data Validity
        2. Start and Stop Conditions
        3. Transferring Data
        4. I2C-Compatible Chip Address
        5. Auto-Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1.  DEV_REV
          1. Table 8. DEV_REV Register Field Descriptions
        2.  OTP_REV
          1. Table 9. OTP_REV Register Field Descriptions
        3.  BUCK0_CTRL_1
          1. Table 10. BUCK0_CTRL_1 Register Field Descriptions
        4.  BUCK0_CTRL_2
          1. Table 11. BUCK0_CTRL_2 Register Field Descriptions
        5.  BUCK1_CTRL_1
          1. Table 12. BUCK1_CTRL_1 Register Field Descriptions
        6.  BUCK1_CTRL_2
          1. Table 13. BUCK1_CTRL_2 Register Field Descriptions
        7.  BUCK0_VOUT
          1. Table 14. BUCK0_VOUT Register Field Descriptions
        8.  BUCK1_VOUT
          1. Table 15. BUCK1_VOUT Register Field Descriptions
        9.  LDO0_CTRL
          1. Table 16. LDO0_CTRL Register Field Descriptions
        10. LDO1_CTRL
          1. Table 17. LDO1_CTRL Register Field Descriptions
        11. LDO0_VOUT
          1. Table 18. LDO0_VOUT Register Field Descriptions
        12. LDO1_VOUT
          1. Table 19. LDO1_VOUT Register Field Descriptions
        13. BUCK0_DELAY
          1. Table 20. BUCK0_DELAY Register Field Descriptions
        14. BUCK1_DELAY
          1. Table 21. BUCK1_DELAY Register Field Descriptions
        15. LDO0_DELAY
          1. Table 22. LDO0_DELAY Register Field Descriptions
        16. LDO1_DELAY
          1. Table 23. LDO1_DELAY Register Field Descriptions
        17. GPO_DELAY
          1. Table 24. GPO_DELAY Register Field Descriptions
        18. GPO2_DELAY
          1. Table 25. GPO2_DELAY Register Field Descriptions
        19. GPO_CTRL
          1. Table 26. GPO_CTRL Register Field Descriptions
        20. CONFIG
          1. Table 27. CONFIG Register Field Descriptions
        21. PLL_CTRL
          1. Table 28. PLL_CTRL Register Field Descriptions
        22. PGOOD_CTRL_1
          1. Table 29. PGOOD_CTRL_1 Register Field Descriptions
        23. PGOOD_CTRL_2
          1. Table 30. PGOOD_CTRL_2 Register Field Descriptions
        24. PG_FAULT
          1. Table 31. PG_FAULT Register Field Descriptions
        25. RESET
          1. Table 32. RESET Register Field Descriptions
        26. INT_TOP_1
          1. Table 33. INT_TOP_1 Register Field Descriptions
        27. INT_TOP_2
          1. Table 34. INT_TOP_2 Register Field Descriptions
        28. INT_BUCK
          1. Table 35. INT_BUCK Register Field Descriptions
        29. INT_LDO
          1. Table 36. INT_LDO Register Field Descriptions
        30. TOP_STAT
          1. Table 37. TOP_STAT Register Field Descriptions
        31. BUCK_STAT
          1. Table 38. BUCK_STAT Register Field Descriptions
        32. LDO_STAT
          1. Table 39. LDO_STAT Register Field Descriptions
        33. TOP_MASK_1
          1. Table 40. TOP_MASK_1 Register Field Descriptions
        34. TOP_MASK_2
          1. Table 41. TOP_MASK_2 Register Field Descriptions
        35. BUCK_MASK
          1. Table 42. BUCK_MASK Register Field Descriptions
        36. LDO_MASK
          1. Table 43. LDO_MASK Register Field Descriptions
        37. SEL_I_LOAD
          1. Table 44. SEL_I_LOAD Register Field Descriptions
        38. I_LOAD_2
          1. Table 45. I_LOAD_2 Register Field Descriptions
        39. I_LOAD_1
          1. Table 46. I_LOAD_1 Register Field Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
        1. Inductor Selection
        2. Buck Input Capacitor Selection
        3. Buck Output Capacitor Selection
        4. LDO Input Capacitor Selection
        5. LDO Output Capacitor Selection
        6. Current Limit vs. Maximum Output Current
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

The high frequency and large switching currents of the LP8733xx make the choice of layout important. Good power supply results only occur when care is given to proper design and layout. Layout affects noise pickup and generation and can cause a good design to perform with less-than-expected results. With a range of output currents from milliamps to several amps, good power supply layout is much more difficult than most general PCB design. Use the following steps as a reference to ensure the device is stable and maintains proper voltage and current regulation across its intended operating voltage and current range.

  1. Place CIN as close as possible to the VIN_Bx pin and the PGND_Bx pin. Route the VIN trace wide and thick to avoid IR drops. The trace between the positive node of the input capacitor and the VIN_Bx pins of LP8733xx, as well as the trace between the negative node of the input capacitor and the power PGND_Bx pins, must be kept as short as possible. The input capacitance provides a low-impedance voltage source for the switching converter. The inductance of the connection is the most important parameter of a local decoupling capacitor — parasitic inductance on these traces must be kept as small as possible for proper device operation. The parasitic inductance can be reduced by using a ground plane as close as possible to the top layer by using thin dielectric layer between the top layer and the ground plane.
  2. The output filter, consisting of L and COUT, converts the switching signal at SW_Bx to the noiseless output voltage. The output filter must be placed as close as possible to the device, keeping the switch node small for best EMI behavior. Route the traces between the output capacitors of the LP8733xx and the input capacitors of the load direct and wide to avoid losses due to the IR drop.
  3. Input for analog blocks (VANA and AGND) must be isolated from noisy signals. Connect VANA directly to a quiet system voltage node and AGND to a quiet ground point where no IR drop occurs. Place the decoupling capacitor as close as possible to the VANA pin.
  4. If remote voltage sensing can be used for the load, connect the LP8733xx feedback pins FB_Bx to the respective sense pins on the load capacitor. The sense lines are susceptible to noise. They must be kept away from noisy signals such as PGND_Bx, VIN_Bx, and SW_Bx, as well as high bandwidth signals such as the I2C. Avoid both capacitive and inductive coupling by keeping the sense lines short and direct, and close to each other. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane if possible. If series resistors are used for load current measurement, place them after connection of the voltage feedback.
  5. PGND_Bx, VIN_Bx and SW_Bx must be routed on thick layers. They must not surround inner signal layers which are not able to withstand interference from noisy PGND_Bx, VIN_Bx and SW_Bx.
  6. LDO performance (PSRR, noise, and transient response) depend on the layout of the PCB. Best performance is achieved by placing CIN and COUT as close to the LP8733xx device as practical. The ground connections for CIN and COUT must be back to the LP8733xx AGND with as wide and as short of a copper trace as is practical and with multiple vias if routing is done on other layer. Avoid connections using long trace lengths, narrow trace widths, or connection through small via. These add parasitic inductances and resistance that results in inferior performance, especially during transient conditions.

Due to the small package of this converter and the overall small solution size, the thermal performance of the PCB layout is important. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of a given component. Proper PCB layout, focusing on thermal performance, results in lower die temperatures. Wide power traces can sink dissipated heat. This can be improved further on multi-layer PCB designs with vias to different planes. This results in reduced junction-to-ambient (RθJA) and junction-to-board (RθJB) thermal resistances, thereby reducing the device junction temperature, TJ. TI strongly recommends performance of a careful system-level 2D or full 3D dynamic thermal analysis at the beginning product design process by using a thermal modeling analysis software.