SNVSBK2 September   2019 LP8733

PRODUCTION DATA.  

  1. Features
    1.     Simplified Schematic
  2. Applications
  3. Description
    1.     DC/DC Efficiency vs Output Current
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Serial Bus Timing Parameters
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DC/DC Converters
        1. 7.3.1.1 Overview
        2. 7.3.1.2 Dual-Phase Operation and Phase-Adding/Shedding
        3. 7.3.1.3 Transition Between PWM and PFM Modes
        4. 7.3.1.4 Dual-Phase Switcher Configurations
        5. 7.3.1.5 Buck Converter Load Current Measurement
        6. 7.3.1.6 Spread-Spectrum Mode
      2. 7.3.2  Sync Clock Functionality
      3. 7.3.3  Low-Dropout Linear Regulators (LDOs)
      4. 7.3.4  Power-Up
      5. 7.3.5  Regulator Control
        1. 7.3.5.1 Enabling and Disabling Regulators
        2. 7.3.5.2 Changing Output Voltage
      6. 7.3.6  Enable and Disable Sequences
      7. 7.3.7  Device Reset Scenarios
      8. 7.3.8  Diagnosis and Protection Features
        1. 7.3.8.1 Power-Good Information (PGOOD pin)
          1. 7.3.8.1.1 PGOOD Pin Gated Mode
          2. 7.3.8.1.2 PGOOD Pin Continuous Mode
        2. 7.3.8.2 Warnings for Diagnosis (Interrupt)
          1. 7.3.8.2.1 Output Power Limit
          2. 7.3.8.2.2 Thermal Warning
        3. 7.3.8.3 Protection (Regulator Disable)
          1. 7.3.8.3.1 Short-Circuit and Overload Protection
          2. 7.3.8.3.2 Overvoltage Protection
          3. 7.3.8.3.3 Thermal Shutdown
        4. 7.3.8.4 Fault (Power Down)
          1. 7.3.8.4.1 Undervoltage Lockout
      9. 7.3.9  Operation of the GPO Signals
      10. 7.3.10 Digital Signal Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start and Stop Conditions
        3. 7.5.1.3 Transferring Data
        4. 7.5.1.4 I2C-Compatible Chip Address
        5. 7.5.1.5 Auto-Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1. 7.6.1.1  DEV_REV
          1. Table 8. DEV_REV Register Field Descriptions
        2. 7.6.1.2  OTP_REV
          1. Table 9. OTP_REV Register Field Descriptions
        3. 7.6.1.3  BUCK0_CTRL_1
          1. Table 10. BUCK0_CTRL_1 Register Field Descriptions
        4. 7.6.1.4  BUCK0_CTRL_2
          1. Table 11. BUCK0_CTRL_2 Register Field Descriptions
        5. 7.6.1.5  BUCK1_CTRL_1
          1. Table 12. BUCK1_CTRL_1 Register Field Descriptions
        6. 7.6.1.6  BUCK1_CTRL_2
          1. Table 13. BUCK1_CTRL_2 Register Field Descriptions
        7. 7.6.1.7  BUCK0_VOUT
          1. Table 14. BUCK0_VOUT Register Field Descriptions
        8. 7.6.1.8  BUCK1_VOUT
          1. Table 15. BUCK1_VOUT Register Field Descriptions
        9. 7.6.1.9  LDO0_CTRL
          1. Table 16. LDO0_CTRL Register Field Descriptions
        10. 7.6.1.10 LDO1_CTRL
          1. Table 17. LDO1_CTRL Register Field Descriptions
        11. 7.6.1.11 LDO0_VOUT
          1. Table 18. LDO0_VOUT Register Field Descriptions
        12. 7.6.1.12 LDO1_VOUT
          1. Table 19. LDO1_VOUT Register Field Descriptions
        13. 7.6.1.13 BUCK0_DELAY
          1. Table 20. BUCK0_DELAY Register Field Descriptions
        14. 7.6.1.14 BUCK1_DELAY
          1. Table 21. BUCK1_DELAY Register Field Descriptions
        15. 7.6.1.15 LDO0_DELAY
          1. Table 22. LDO0_DELAY Register Field Descriptions
        16. 7.6.1.16 LDO1_DELAY
          1. Table 23. LDO1_DELAY Register Field Descriptions
        17. 7.6.1.17 GPO_DELAY
          1. Table 24. GPO_DELAY Register Field Descriptions
        18. 7.6.1.18 GPO2_DELAY
          1. Table 25. GPO2_DELAY Register Field Descriptions
        19. 7.6.1.19 GPO_CTRL
          1. Table 26. GPO_CTRL Register Field Descriptions
        20. 7.6.1.20 CONFIG
          1. Table 27. CONFIG Register Field Descriptions
        21. 7.6.1.21 PLL_CTRL
          1. Table 28. PLL_CTRL Register Field Descriptions
        22. 7.6.1.22 PGOOD_CTRL_1
          1. Table 29. PGOOD_CTRL_1 Register Field Descriptions
        23. 7.6.1.23 PGOOD_CTRL_2
          1. Table 30. PGOOD_CTRL_2 Register Field Descriptions
        24. 7.6.1.24 PG_FAULT
          1. Table 31. PG_FAULT Register Field Descriptions
        25. 7.6.1.25 RESET
          1. Table 32. RESET Register Field Descriptions
        26. 7.6.1.26 INT_TOP_1
          1. Table 33. INT_TOP_1 Register Field Descriptions
        27. 7.6.1.27 INT_TOP_2
          1. Table 34. INT_TOP_2 Register Field Descriptions
        28. 7.6.1.28 INT_BUCK
          1. Table 35. INT_BUCK Register Field Descriptions
        29. 7.6.1.29 INT_LDO
          1. Table 36. INT_LDO Register Field Descriptions
        30. 7.6.1.30 TOP_STAT
          1. Table 37. TOP_STAT Register Field Descriptions
        31. 7.6.1.31 BUCK_STAT
          1. Table 38. BUCK_STAT Register Field Descriptions
        32. 7.6.1.32 LDO_STAT
          1. Table 39. LDO_STAT Register Field Descriptions
        33. 7.6.1.33 TOP_MASK_1
          1. Table 40. TOP_MASK_1 Register Field Descriptions
        34. 7.6.1.34 TOP_MASK_2
          1. Table 41. TOP_MASK_2 Register Field Descriptions
        35. 7.6.1.35 BUCK_MASK
          1. Table 42. BUCK_MASK Register Field Descriptions
        36. 7.6.1.36 LDO_MASK
          1. Table 43. LDO_MASK Register Field Descriptions
        37. 7.6.1.37 SEL_I_LOAD
          1. Table 44. SEL_I_LOAD Register Field Descriptions
        38. 7.6.1.38 I_LOAD_2
          1. Table 45. I_LOAD_2 Register Field Descriptions
        39. 7.6.1.39 I_LOAD_1
          1. Table 46. I_LOAD_1 Register Field Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Inductor Selection
        2. 8.2.1.2 Buck Input Capacitor Selection
        3. 8.2.1.3 Buck Output Capacitor Selection
        4. 8.2.1.4 LDO Input Capacitor Selection
        5. 8.2.1.5 LDO Output Capacitor Selection
        6. 8.2.1.6 Current Limit vs. Maximum Output Current
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Overview

The LP8733xx includes two step-down DC/DC converter cores. The cores are designed for flexibility; most of the functions are programmable, thus giving a possibility to optimize the regulator operation for each application. The cores can be configured either for a dual-phase single output configuration or for a single-phase dual output configuration. The buck regulators deliver 0.7-V to 3.36-V regulated voltage rails from a 2.8-V to 5.5-V supply voltage.

The LP8733xx has the following features:

  • DVS support with programmable slew rate
  • Automatic mode control based on the loading (PFM or PWM mode)
  • Forced PWM mode option
  • Optional external clock input to minimize crosstalk
  • Optional spread-spectrum technique to reduce EMI
  • Phase control for optimized EMI
  • Synchronous rectification
  • Current mode loop with PI compensator
  • Soft start
  • Power Good flag with maskable interrupt
  • Power Good signal (PGOOD) with selectable sources
  • Average output current sensing (for PFM entry, phase shedding and adding in dual-phase configuration, and load current measurement)
  • Current balancing between the phases of the converter in dual-phase configuration
  • Differential voltage sensing from point of the load in dual-phase configuration
  • Dynamic phase shedding and adding, each output being phase shifted in dual-phase configuration

The following parameters can be programmed via registers, the default values are set by OTP bits:

  • Output voltage
  • Forced PWM operation
  • Forced dual-phase operation (forces also the PWM operation)
  • Switch current limit
  • Output voltage slew rate
  • Enable and disable delays

There are two modes of operation for the buck converter, depending on the output current required: pulse-width modulation (PWM) and pulse-frequency modulation (PFM). The converter operates in PWM mode at high load currents of approximately 600 mA or higher. When operating in PWM mode in dual-phase configuration the phases are automatically added and shedded based on the load current level. Lighter output current loads cause the converter to automatically switch into PFM mode for reduced current consumption when forced PWM mode is disabled. The forced PWM mode can be selected to maintain fixed switching frequency at all load current levels.

A block diagram of a single core is shown in Figure 8.

LP8733 Detailed_Block.gifFigure 8. Detailed Block Diagram Showing One Core