The output capacitor C_{OUT_BUCK0} and C_{OUT_BUCK1} are shown in Section 8.2. A ceramic local output capacitor of 22 μF is required per phase. Use ceramic capacitors, X7R type; do not use Y5V or F. DC bias voltage characteristics of ceramic capacitors must be considered. The output filter capacitor smooths out current flow from the inductor to the load, which helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR and ESL to perform these functions. The minimum effective output capacitance to ensure good performance is 10 μF per phase, including the DC voltage rolloff, tolerances, aging, and temperature effects.

The output voltage ripple is caused by the charging and discharging of the output capacitor and due to its R_ESR. The R_ESR is frequency dependent (and temperature dependent); ensure the value used for selection process is at the switching frequency of the part. See Table 8-3.

POL capacitors can be used to improve load transient performance and to decrease the ripple voltage. A higher output capacitance improves the load step behavior, reduces the output voltage ripple, and decreases the PFM switching frequency. However, output capacitance higher than 150 μF per phase is not necessarily of any benefit. The output capacitor may be the limiting factor in the output voltage ramp, see Section 6 for maximum output capacitance for different slew-rate settings. For large output capacitors, the output voltage might be slower than the programmed ramp rate at voltage transitions, because of the higher energy stored on the output capacitance. Also at start-up, the time required to charge the output capacitor to target value might be longer. At shutdown, the output voltage is discharged to a 0.6 V level using forced-PWM operation. This can increase the input voltage if the load current is small and the output capacitor is large compared to input capacitor. Below the 0.6 V level, the output capacitor is discharged by the internal discharge resistor, and with large capacitor more time is required to settle V_OUT down as a consequence of the increased time constant.