SNVSC24 April 2021 LP8758-EA
The converter core's output voltage can be changed by the ENx pin (voltage levels defined by the BUCKx_VOUT and BUCKx_FLOOR_VOUT registers) or by writing to the BUCKx_VOUT and BUCKx_FLOOR_VOUT registers. The voltage change is always slew-rate controlled, and the slew-rate is defined by the BUCKx_CTRL2.SLEW_RATEx[2:0] bits. During voltage change the Forced PWM mode is used automatically. When the programmed output voltage is achieved, the mode becomes the one defined by load current, and the BUCKx_CTRL1.BUCKx_FPWM bit.