SNVSC24 April   2021 LP8758-EA

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Serial Bus Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Buck Information
        1. 7.1.1.1 Operating Modes
        2. 7.1.1.2 Programmability
        3. 7.1.1.3 Features
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Overview
        1. 7.3.1.1 Transition Between PWM and PFM Modes
        2. 7.3.1.2 Buck Converter Load Current Measurement
        3. 7.3.1.3 Spread-Spectrum Mode
      2. 7.3.2 Power-Up
      3. 7.3.3 Regulator Control
        1. 7.3.3.1 Enabling and Disabling
        2. 7.3.3.2 Changing Output Voltage
      4. 7.3.4 Device Reset Scenarios
      5. 7.3.5 Diagnosis and Protection Features
        1. 7.3.5.1 Warnings for Diagnosis (Interrupt)
          1. 7.3.5.1.1 Output Current Limit
          2. 7.3.5.1.2 Thermal Warning
        2. 7.3.5.2 Protection (Regulator Disable)
          1. 7.3.5.2.1 Short-Circuit and Overload Protection
          2. 7.3.5.2.2 Thermal Shutdown
        3. 7.3.5.3 Fault (Power Down)
          1. 7.3.5.3.1 Undervoltage Lockout
      6. 7.3.6 Digital Signal Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start and Stop Conditions
        3. 7.5.1.3 Transferring Data
        4. 7.5.1.4 I2C-Compatible Chip Address
        5. 7.5.1.5 Auto Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1. 7.6.1.1  OTP_REV
        2. 7.6.1.2  BUCK0_CTRL1
        3. 7.6.1.3  BUCK0_CTRL2
        4. 7.6.1.4  BUCK1_CTRL1
        5. 7.6.1.5  BUCK1_CTRL2
        6. 7.6.1.6  BUCK2_CTRL1
        7. 7.6.1.7  BUCK2_CTRL2
        8. 7.6.1.8  BUCK3_CTRL1
        9. 7.6.1.9  BUCK3_CTRL2
        10. 7.6.1.10 BUCK0_VOUT
        11. 7.6.1.11 BUCK0_FLOOR_VOUT
        12. 7.6.1.12 BUCK1_VOUT
        13. 7.6.1.13 BUCK1_FLOOR_VOUT
        14. 7.6.1.14 BUCK2_VOUT
        15. 7.6.1.15 BUCK2_FLOOR_VOUT
        16. 7.6.1.16 BUCK3_VOUT
        17. 7.6.1.17 BUCK3_FLOOR_VOUT
        18. 7.6.1.18 BUCK0_DELAY
        19. 7.6.1.19 BUCK1_DELAY
        20. 7.6.1.20 BUCK2_DELAY
        21. 7.6.1.21 BUCK3_DELAY
        22. 7.6.1.22 RESET
        23. 7.6.1.23 CONFIG
        24. 7.6.1.24 INT_TOP
        25. 7.6.1.25 INT_BUCK_0_1
        26. 7.6.1.26 INT_BUCK_2_3
        27. 7.6.1.27 TOP_STAT
        28. 7.6.1.28 BUCK_0_1_STAT
        29. 7.6.1.29 BUCK_2_3_STAT
        30. 7.6.1.30 TOP_MASK
        31. 7.6.1.31 BUCK_0_1_MASK
        32. 7.6.1.32 BUCK_2_3_MASK
        33. 7.6.1.33 SEL_I_LOAD
        34. 7.6.1.34 I_LOAD_2
        35. 7.6.1.35 I_LOAD_1
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Application Components
          1. 8.2.2.1.1 Inductor Selection
          2. 8.2.2.1.2 Input Capacitor Selection
          3. 8.2.2.1.3 Output Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6.1 Register Descriptions

The LP8758-EA is controlled by a set of registers through the serial interface port. The device registers, their addresses and their abbreviations are listed in Table 7-5. A more detailed description is given in sections Section 7.6.1.1 to Section 7.6.1.35.

The asterisk (*) marking indicates register bits which are updated from OTP memory during READ OTP state.

Table 7-5 Summary of LP8758-EA Control Registers
AddrRegisterRead / WriteD7D6D5D4D3D2D1D0
0x01OTP_REVROTP_ID[7:0]
0x02BUCK0_
CTRL1		R/WEN_BUCK0EN_PIN_
CTRL0		EN_PIN_
SELECT0		EN_ROOF
_FLOOR0		EN_RDIS0ReservedBUCK0_
FPWM		Reserved
0x03BUCK0_
CTRL2		R/WReservedILIM0[2:0]SLEW_RATE0[2:0]
0x04BUCK1_
CTRL1		R/WEN_BUCK1EN_PIN_
CTRL1		EN_PIN_
SELECT1		EN_ROOF
_FLOOR1		EN_RDIS1ReservedBUCK1_
FPWM		Reserved
0x05BUCK1_
CTRL2		R/WReservedILIM1[2:0]SLEW_RATE1[2:0]
0x06BUCK2_
CTRL1		R/WEN_BUCK2EN_PIN_
CTRL2		EN_PIN_
SELECT2		EN_ROOF
_FLOOR2		EN_RDIS2ReservedBUCK2_
FPWM		Reserved
0x07BUCK2_
CTRL2		R/WReservedILIM2[2:0]SLEW_RATE2[2:0]
0x08BUCK3_
CTRL1		R/WEN_BUCK3EN_PIN_
CTRL3		EN_PIN_
SELECT3		EN_ROOF
_FLOOR3		EN_RDIS3ReservedBUCK3_
FPWM		Reserved
0x09BUCK3_
CTRL2		R/WReservedILIM3[2:0]SLEW_RATE3[2:0]
0x0ABUCK0_
VOUT		R/WBUCK0_VSET[7:0]
0x0BBUCK0_
FLOOR_
VOUT		R/WBUCK0_FLOOR_VSET[7:0]
0x0CBUCK1_
VOUT		R/WBUCK1_VSET[7:0]
0x0DBUCK1_
FLOOR_
VOUT		R/WBUCK1_FLOOR_VSET[7:0]
0x0EBUCK2_
VOUT		R/WBUCK2_VSET[7:0]
0x0FBUCK2_
FLOOR_
VOUT		R/WBUCK2_FLOOR_VSET[7:0]
0x10BUCK3_
VOUT		R/WBUCK3_VSET[7:0]
0x11BUCK3_
FLOOR_
VOUT		R/WBUCK3_FLOOR_VSET[7:0]
0x12BUCK0_
DELAY		R/WBUCK0_SHUTDOWN_DELAY[3:0]BUCK0_STARTUP_DELAY[3:0]
0x13BUCK1_
DELAY		R/WBUCK1_SHUTDOWN_DELAY[3:0]BUCK1_STARTUP_DELAY[3:0]
0x14BUCK2_
DELAY		R/WBUCK2_SHUTDOWN_DELAY[3:0]BUCK2_STARTUP_DELAY[3:0]
0x15BUCK3_
DELAY		R/WBUCK3_SHUTDOWN_DELAY[3:0]BUCK3_STARTUP_DELAY[3:0]
0x16RESETR/WReservedSW_
RESET
0x17CONFIGR/WReservedTDIE
_WARN
_LEVEL		EN2_PDEN1_PDEN_
SPREAD
_SPEC
0x18INT_TOPR/WINT_
BUCK3		INT_
BUCK2		INT_
BUCK1		INT_
BUCK0		TDIE_SDTDIE_
WARN		RESET_
REG		I_LOAD_
READY
0x19INT_BUCK_0_1R/WReservedBUCK1_
PG_INT		BUCK1_
SC_INT		BUCK1_
ILIM_INT		ReservedBUCK0_
PG_INT		BUCK0_
SC_INT		BUCK0_
ILIM_INT
0x1AINT_BUCK_2_3R/WReservedBUCK3_
PG_INT		BUCK3_
SC_INT		BUCK3_
ILIM_INT		ReservedBUCK2_
PG_INT		BUCK2_
SC_INT		BUCK2_
ILIM_INT
0x1BTOP_
STAT		RReservedTDIE_SD
_STAT		TDIE_
WARN_
STAT		Reserved
0x1CBUCK_0_1_STATRBUCK1_
STAT		BUCK1_
PG_STAT		ReservedBUCK1_
ILIM_
STAT		BUCK0_
STAT		BUCK0_
PG_STAT		ReservedBUCK0_
ILIM_
STAT
0x1DBUCK_2_3_STATRBUCK3_
STAT		BUCK3_
PG_STAT		ReservedBUCK3_
ILIM_STAT		BUCK2_
STAT		BUCK2_
PG_STAT		ReservedBUCK2_
ILIM_STAT
0x1ETOP_
MASK		R/WReservedTDIE_WARN_MASKRESET_
REG_MASK		I_LOAD_
READY_
MASK
0x1FBUCK_0_1_MASKR/WReservedBUCK1_
PG_MASK		ReservedBUCK1_
ILIM_
MASK		ReservedBUCK0_
PG_MASK		ReservedBUCK0_
ILIM_
MASK
0x20BUCK_2_3_MASKR/WReservedBUCK3_
PG_MASK		ReservedBUCK3_
ILIM_
MASK		ReservedBUCK2_
PG_MASK		ReservedBUCK2_
ILIM_
MASK
0x21SEL_I_
LOAD		R/WReservedLOAD_CURRENT_
BUCK_SELECT[1:0]
0x22I_LOAD_2R/WReservedBUCK_LOAD_CURRENT[9:8]
0x23I_LOAD_1R/WBUCK_LOAD_CURRENT[7:0]