The LP8764-Q1 device integrates ten configurable general-purpose I/Os that are multiplexed with alternative features as listed in Pin Configuration and Functions.

For GPIOs characteristics, refer to Electrical Characteristics tables for Digital Input Signal Parameters and Digital Output Signal Parameters.

When configured as primary functions, all GPIOs are controlled through the following set of registers bits under the individual GPIOn_CONF register.

• GPIOn_DEGLITCH_EN: Enables the 8 µs deglitch time for each GPIO pin (input)
• GPIOn_PU_PD_EN: Enables the internal pull up or pull down resistor connected to each GPIO pin
• GPIOn_PU_SEL: Selects the pull up or the pull down resistor to be connected when GPIOn_PU_PD_EN = '1'. '1' = pull-up resistor selected, '0' = pull-down resistor selected
• GPIOn_OD: Configures the GPIO pin (output) as: '1' = open drain, '0' = push-pull
• GPIOn_DIR: Configures the input or output direction of each GPIO pin

Each GPIO event can generate an interrupt on a rising edge, falling edge, or both, configured through the GPIOn_FALL_MASK and the GPIOn_RISE_MASK register bits. A GPIO-interrupt applies when the primary function (general-purpose I/O) has been selected and also for the following alternative functions:

• ENABLE
• EN_DRV
• nRSTOUT
• nRSTOUT_SOC
• PGOOD
• nERR_MCU
• TRIG_WDOG
• NSLEEP1, NSLEEP2
• WKUP1, WKUP2

The GPIOn_SEL[2:0] register bits under the GPIOn_CONF registers control the selection between a primary and an alternative function. When a pre-defined function is selected, some predetermined IO characteristics (such as pullup, pulldown, push-pull or open drain) for the pin are enforced regardless of the settings of the associated GPIO configuration register. Please note that if the GPIOn_SEL[2:0] is changed during device operation, a signal glitch may occur, which may cause digital malfunction, especially if it involves a clock signal such as SCL_I2C2, SCL_SPMI, SYNCCLKIN, or SYNCCLKOUT. Please refer to Digital Signal Descriptions for more detail on the predetermined IO characteristics for each pre-defined digital interface function.

All GPIOs can be configured as a wake-up input when it is configured as a WKUP1 or a WKUP2 signal. All GPIOs can also be configured as a NSLEEP1 or a NSLEEP2 input. For more information regarding the usage of the NSLEEPx pins and the WKUPx pins, please refer to Section 8.4.2.4.2.1 and Section 8.4.2.4.2.2.

Any of the GPIO pin can also be configured as part of the power-up sequence to enable external devices such as external BUCKs when it is configured as a general-purpose output port.

The nINT pin and the GPIO pins assigned as EN_DRV , nRSTOUT and nRSTOUT_SOC have readback monitoring to detect errors on the signals. The monitoring of the GPIO pin assigned as EN_DRV checks for mismatch in both low and high levels. For the nINT pin and the GPIO pins assigned as nRSTOUT and nRSTOUT_SOC, the readback monitoring only checks for mismatches in the low level, therefore it is allowed to combine these signals with other external pull-down sources. The readback mismatch is continuously monitored without deglitch circuitry during operation, and the monitoring is gated for t_{gate_readback} period when the signal state is changed or when a new function is selected for the GPIO pin with the GPIOn_SEL bits. NINT_READBACK_INT, EN_DRV_READBACK_INT, NRSTOUT_READBACK_INT, and NRSTOUT_SOC_READBACK_INT are the interrupt bits that are set in an event of a readback mismatch for these pins, respectively.