The LP8764-Q1 device is a power-management integrated circuit (PMIC), available in a 32-pin, 0.5-mm pitch, 5.5-mm × 5-mm QFN HotRod package. The device is designed for powering embedded systems or system on chip (SoC) in Automotive or Industrial applications. The device provides four configurable buck converter rails, with ability to combine outputs in multi-phase mode. All converters can support up to 5-A per phase resulting up to 20-A in four-phase configuration, 15-A in 3-phase configuration, and 10-A in dual-phase configuration. All buck converters have the capability to sink up to 1 A, and support dynamic voltage scaling. Double buffered voltage scaling registers enable each BUCK to transition to a different voltages during operation by SPI, I²C or state transition. A DPLL enables the BUCK converters to synchronizing to an external clock input, with phase delays between the output rails.

Two I²C interface channels or one SPI channel can be used to configure the power rails and the power state of the LP8764-Q1 device. I²C channel 1 (I2C1) is the main channel with access to the registers that control the configurable power sequencer, the states and the outputs of power rails, and the device operating states. I²C channel 2 (I2C2), which is available through GPIO2 and GPIO3 pins, is dedicated for accessing the Q&A Watchdog communication registers. When the SPI is configured instead of the two I²C interfaces, the SPI can access all of the registers, including the Q&A Watchdog registers. An NVM option is available to enable I2C1 to access all of the registers as well, including the Q&A Watchdog registers.

The LP8764-Q1 device includes an internal RC oscillator to sequence all resources during power up and power down. An internal LDO (LDOVINT) generates the supply for the entire digital circuitry of the device as soon as the external input supply is available through the VCCA input.

LP8764-Q1 device has ten GPIOs each with multiple functions and configurable features. All of the GPIOs, when configured as a general purpose output pin, can be included in the power-up and power-down sequence and used as enable signals for external resources. In addition, each GPIO can be configured as a wake-up input or a sleep mode trigger. The default configuration of the GPIO port comes from the NVM memory, and can be re-configured by software if the external connection permits.

The LP8764-Q1 device includes a Q&A watchdog to monitor software lockup, and a system error monitoring input (nERR_MCU) with fault injection option to monitor the lock-step signal of the attached MCU. The device includes protection and diagnostic mechanisms such as short-circuit protection, thermal monitoring and shutdown. The PMIC can notify the processor of these events through the interrupt signal, allowing the processor to take action in response.

An SPMI interface is included in the LP8764-Q1 device to distribute power state information to at most five satellite PMICs, thus enabling synchronous power state transition across multiple PMICs in the application system. This feature allows the consolidation of IO control signals from up to six PMICs powering the system into one primary LP8764-Q1 PMIC.