SNVSAL1C December 2017 – June 2021 LP87702-Q1
The LP87702-Q1 is controlled by a set of registers through the system serial interface port. This register map describes the default values for the bits which are not read from OTP memory. The asterisk (*) marking indicates the register bits which are updated from the OTP memory during the READ OTP state. OTP values for each orderable part number are described in a separate technical reference manual TRM.