SLLS047M February   1989  – November 2014 MAX232

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics –– Device
    6. 7.6 Electrical Characteristics –– Driver
    7. 7.7 Electrical Characteristics –– Receiver
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power
      2. 9.3.2 RS232 Driver
      3. 9.3.3 RS232 Receiver
    4. 9.4 Device Functional Modes
      1. 9.4.1 VCC powered by 5V
      2. 9.4.2 VCC unpowered
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • NS|16
  • DW|16
  • N|16
  • D|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.8 Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS(1) MIN TYP(1) MAX UNIT
SR Driver slew rate RL = 3 kΩ to 7 kΩ, see Figure 4 30 V/μs
SR(t) Driver transition region slew rate see Figure 5 3 V/μs
Data rate One TOUT switching 120 kbit/s
tPLH®) Receiver propagation delay time, low- to high-level output TTL load, see Figure 3 500 ns
tPHL®) Receiver propagation delay time, high- to low-level output TTL load, see Figure 3 500 ns
(1) Test conditions are C1–C4 = 1 μF at VCC = 5 V ± 0.5 V.