SLLSFH8A August   2021  – December 2021 MCT8316A

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Output Stage
      2. 8.3.2  Device Interface Modes
        1. 8.3.2.1 Interface - Control and Monitoring
        2. 8.3.2.2 I2C Interface
        3. 8.3.2.3 Hardware Interface - Pin Configuration
      3. 8.3.3  Step-Down Mixed-Mode Buck Regulator
        1. 8.3.3.1 Buck in Inductor Mode
        2. 8.3.3.2 Buck in Resistor mode
        3. 8.3.3.3 Buck Regulator with External LDO
        4. 8.3.3.4 AVDD Power Sequencing from Buck Regulator
        5. 8.3.3.5 Mixed Mode Buck Operation and Control
        6. 8.3.3.6 Buck Undervoltage Protection
        7. 8.3.3.7 Buck Overcurrent Protection
      4. 8.3.4  AVDD Linear Voltage Regulator
      5. 8.3.5  Charge Pump
      6. 8.3.6  Slew Rate Control
      7. 8.3.7  Cross Conduction (Dead Time)
      8. 8.3.8  SPEED Control
        1. 8.3.8.1 Analog-Mode Speed Control
        2. 8.3.8.2 PWM-Mode Speed Control
        3. 8.3.8.3 I2C based Speed Control
        4. 8.3.8.4 Frequency-Mode Speed Control
      9. 8.3.9  Starting the Motor Under Different Initial Conditions
        1. 8.3.9.1 Case 1 – Motor is Stationary
        2. 8.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 8.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 8.3.10 Motor Start Sequence (MSS)
        1. 8.3.10.1 Initial Speed Detect (ISD)
        2. 8.3.10.2 Motor Resynchronization
        3. 8.3.10.3 Reverse Drive
        4. 8.3.10.4 Motor Start-up
          1. 8.3.10.4.1 Align
          2. 8.3.10.4.2 Double Align
          3. 8.3.10.4.3 Initial Position Detection (IPD)
            1. 8.3.10.4.3.1 IPD Operation
            2. 8.3.10.4.3.2 IPD Release Mode
            3. 8.3.10.4.3.3 IPD Advance Angle
          4. 8.3.10.4.4 Slow First Cycle Startup
          5. 8.3.10.4.5 Open loop
          6. 8.3.10.4.6 Transition from Open to Closed Loop
      11. 8.3.11 Closed Loop Operation
        1. 8.3.11.1 120o Commutation
          1. 8.3.11.1.1 High-Side Modulation
          2. 8.3.11.1.2 Low-Side Modulation
          3. 8.3.11.1.3 Mixed Modulation
        2. 8.3.11.2 Variable Commutation (Available only in MCT8316AV)
        3. 8.3.11.3 Lead Angle Control
        4. 8.3.11.4 Closed loop accelerate
      12. 8.3.12 Speed Loop (Available only in MCT8316AV)
      13. 8.3.13 Input Power Regulation (Available only in MCT8316AV)
      14. 8.3.14 Anti-Voltage Surge (AVS)
      15. 8.3.15 Output PWM Switching Frequency
      16. 8.3.16 Fast Start-up (< 50 ms)
        1. 8.3.16.1 BEMF Threshold
        2. 8.3.16.2 Dynamic Degauss
      17. 8.3.17 Fast Deceleration
      18. 8.3.18 Active Demagnetization
        1. 8.3.18.1 Active Demagnetization in action
      19. 8.3.19 Motor Stop Options
        1. 8.3.19.1 Coast (Hi-Z) Mode
        2. 8.3.19.2 Recirculation Mode
        3. 8.3.19.3 Low-Side Braking
        4. 8.3.19.4 High-Side Braking
        5. 8.3.19.5 Active Spin-Down
      20. 8.3.20 FG Configuration
        1. 8.3.20.1 FG Output Frequency
        2. 8.3.20.2 FG Open-Loop and Lock Behavior
      21. 8.3.21 Protections
        1. 8.3.21.1  VM Supply Undervoltage Lockout
        2. 8.3.21.2  AVDD Undervoltage Lockout (AVDD_UV)
        3. 8.3.21.3  BUCK Undervoltage Lockout (BUCK_UV)
        4. 8.3.21.4  VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 8.3.21.5  Overvoltage Protection (OVP)
        6. 8.3.21.6  Overcurrent Protection (OCP)
          1. 8.3.21.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 8.3.21.6.2 OCP Automatic Retry (OCP_MODE = 01b)
          3. 8.3.21.6.3 OCP Report Only (OCP_MODE = 10b)
          4. 8.3.21.6.4 OCP Disabled (OCP_MODE = 11b)
        7. 8.3.21.7  Buck Overcurrent Protection
        8. 8.3.21.8  Cycle-by-Cycle (CBC) Current Limit (CBC_ILIMIT)
          1. 8.3.21.8.1 CBC_ILIMIT Automatic Recovery next PWM Cycle (CBC_ILIMIT_MODE = 000xb)
          2. 8.3.21.8.2 CBC_ILIMIT Automatic Recovery Threshold Based (CBC_ILIMIT_MODE = 001xb)
          3. 8.3.21.8.3 CBC_ILIMIT Automatic Recovery after 'n' PWM Cycles (CBC_ILIMIT_MODE = 010xb)
          4. 8.3.21.8.4 CBC_ILIMIT Report Only (CBC_ILIMIT_MODE = 0110b)
          5. 8.3.21.8.5 CBC_ILIMIT Disabled (CBC_ILIMIT_MODE = 0111b or 1xxxb)
        9. 8.3.21.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 8.3.21.9.1 LOCK_ILIMIT Latched Shutdown (LOCK_ILIMIT_MODE = 00xxb)
          2. 8.3.21.9.2 LOCK_ILIMIT Automatic Recovery (LOCK_ILIMIT_MODE = 01xxb)
          3. 8.3.21.9.3 LOCK_ILIMIT Report Only (LOCK_ILIMIT_MODE = 1000b)
          4. 8.3.21.9.4 LOCK_ILIMIT Disabled (LOCK_ILIMIT_MODE = 1xx1b)
        10. 8.3.21.10 Thermal Warning (OTW)
        11. 8.3.21.11 Thermal Shutdown (TSD)
        12. 8.3.21.12 Motor Lock (MTR_LCK)
          1. 8.3.21.12.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 8.3.21.12.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 8.3.21.12.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 8.3.21.12.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        13. 8.3.21.13 Motor Lock Detection
          1. 8.3.21.13.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 8.3.21.13.2 Lock 2: Loss of Sync (LOSS_OF_SYNC)
          3. 8.3.21.13.3 Lock3: No-Motor Fault (NO_MTR)
        14. 8.3.21.14 IPD Faults
    4. 8.4 Device Functional Modes
      1. 8.4.1 Functional Modes
        1. 8.4.1.1 Sleep Mode
        2. 8.4.1.2 Standby Mode
        3. 8.4.1.3 Fault Reset (CLR_FLT)
    5. 8.5 External Interface
      1. 8.5.1 DRVOFF Functionality
      2. 8.5.2 DAC outputs
      3. 8.5.3 SOX Output
      4. 8.5.4 Oscillator Source
        1. 8.5.4.1 External Clock Source (Available for MCT8316AV)
      5. 8.5.5 External Watchdog (Available only in MCT836AV)
    6. 8.6 EEPROM access and I2C interface
      1. 8.6.1 EEPROM Access
        1. 8.6.1.1 EEPROM Write
        2. 8.6.1.2 EEPROM Read
      2. 8.6.2 I2C Serial Interface (Available only in MCT8316AV)
        1. 8.6.2.1 I2C Data Word
        2. 8.6.2.2 I2C Write Operation
        3. 8.6.2.3 I2C Read Operation
        4. 8.6.2.4 Examples of MCT8316A I2C Communication Protocol Packets
        5. 8.6.2.5 Internal Buffers
        6. 8.6.2.6 CRC Byte Calculation
    7. 8.7 EEPROM (Non-Volatile) Register Map
      1. 8.7.1 Algorithm_Configuration Registers
      2. 8.7.2 Fault_Configuration Registers
      3. 8.7.3 Hardware_Configuration Registers
      4. 8.7.4 Gate_Driver_Configuration Registers
    8. 8.8 RAM (Volatile) Register Map
      1. 8.8.1 Fault_Status Registers
      2. 8.8.2 System_Status Registers
      3. 8.8.3 Algo_Control Registers
      4. 8.8.4 Device_Control Registers
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application curves
        1. 9.2.1.1 Motor startup
        2. 9.2.1.2 120o and variable commutation
        3. 9.2.1.3 Faster startup time
        4. 9.2.1.4 Setting the BEMF threshold
        5. 9.2.1.5 Maximum speed
        6. 9.2.1.6 Faster deceleration
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
      1. 11.3.1 Power Dissipation
  12. 12Device and Documentation Support
    1. 12.1 Support Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Hardware_Configuration Registers

#HARDWARE_CONFIGURATION_HARDWARE_CONFIGURATION_TABLE_1 lists the memory-mapped registers for the Hardware_Configuration registers. All register offset addresses not listed in #HARDWARE_CONFIGURATION_HARDWARE_CONFIGURATION_TABLE_1 should be considered as reserved locations and the register contents should not be modified.

Table 8-45 HARDWARE_CONFIGURATION Registers
AddressAcronymRegister NameSection
A4hPIN_CONFIG1Hardware pin configuration#HARDWARE_CONFIGURATION_HARDWARE_CONFIGURATION_HARDWARE_CONFIGURATION_PIN_CONFIG1
A6hPIN_CONFIG2Hardware pin configuration#HARDWARE_CONFIGURATION_HARDWARE_CONFIGURATION_HARDWARE_CONFIGURATION_PIN_CONFIG2
A8hDEVICE_CONFIGDevice configuration#HARDWARE_CONFIGURATION_HARDWARE_CONFIGURATION_HARDWARE_CONFIGURATION_DEVICE_CONFIG

Complex bit access types are encoded to fit into small table cells. #HARDWARE_CONFIGURATION_HARDWARE_CONFIGURATION_LEGEND shows the codes that are used for access types in this section.

Table 8-46 Hardware_Configuration Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.7.3.1 PIN_CONFIG1 Register (Address = A4h) [Reset = 00000000h]

PIN_CONFIG1 is shown in #HARDWARE_CONFIGURATION_HARDWARE_CONFIGURATION_HARDWARE_CONFIGURATION_PIN_CONFIG1_FIGURE and described in #HARDWARE_CONFIGURATION_HARDWARE_CONFIGURATION_HARDWARE_CONFIGURATION_PIN_CONFIG1_TABLE.

Return to the Summary Table.

Register to configure hardware pins

Figure 8-69 PIN_CONFIG1 Register
3130292827262524
PARITYDACOUT1_VAR_ADDR
R/W-0hR/W-0h
2322212019181716
DACOUT1_VAR_ADDRDACOUT2_VAR_ADDR
R/W-0hR/W-0h
15141312111098
DACOUT2_VAR_ADDR
R/W-0h
76543210
DACOUT2_VAR_ADDRBRAKE_INPUTDIR_INPUTSPD_CTRL_MODERESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 8-47 PIN_CONFIG1 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-19DACOUT1_VAR_ADDRR/W0h 12-bit address of variable to be monitored
18-7DACOUT2_VAR_ADDRR/W0h 12-bit address of variable to be monitored
6-5BRAKE_INPUTR/W0h Brake input configuration

0h = Hardware Pin BRAKE

1h = Overwrite Hardware pin with Active Brake

2h = Overwrite Hardware pin with brake functionality disabled

3h = N/A

4-3DIR_INPUTR/W0h Direction input configuration

0h = Hardware Pin DIR

1h = Overwrite Hardware pin with clockwise rotation OUTA-OUTB-OUTC

3h = N/A

2-1SPD_CTRL_MODER/W0h Speed input configuration

0h = Analog mode speed Input

1h = PWM Mode Speed Input

2h = I2C Speed Input mode

3h = Frequency based speed Input mode

0RESERVEDR/W0h Reserved

8.7.3.2 PIN_CONFIG2 Register (Address = A6h) [Reset = 00000000h]

PIN_CONFIG2 is shown in #HARDWARE_CONFIGURATION_HARDWARE_CONFIGURATION_HARDWARE_CONFIGURATION_PIN_CONFIG2_FIGURE and described in #HARDWARE_CONFIGURATION_HARDWARE_CONFIGURATION_HARDWARE_CONFIGURATION_PIN_CONFIG2_TABLE.

Return to the Summary Table.

Register to configure hardware pins

Figure 8-70 PIN_CONFIG2 Register
3130292827262524
PARITYDAC_SOX_CONFIGRESERVEDDAC_XTAL_CONFIGRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDSLEEP_TIMEEXT_WD_ENEXT_WD_INPUT
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
EXT_WD_FAULTEXT_WD_FREQRESERVED
R/W-0hR/W-0hR/W-0h
76543210
RESERVED
R/W-0h
Table 8-48 PIN_CONFIG2 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-29DAC_SOX_CONFIGR/W0h Pin 36 configuration

0h = DACOUT2

1h = SOA

2h = SOB

3h = SOC

28RESERVEDR/W0h Reserved
27DAC_XTAL_CONFIGR/W0h Pin 37 and pin 38 configuration

0h = N/A

1h = Pin 37 as DACOUT1 and pin 38 as DACOUT2

26-20RESERVEDR/W0h Reserved
19-18SLEEP_TIMER/W0h Sleep Time

0h = Check low for 50 µs

1h = Check low for 200 µs

2h = Check low for 20 ms

3h = Check low for 200 ms

17EXT_WD_ENR/W0h Enable external watchdog

0h = Disable

1h = Enable

16EXT_WD_INPUTR/W0h External watchdog source

0h = I2C

1h = GPIO

15EXT_WD_FAULTR/W0h External watchdog fault mode

0h = Report only

1h = Latched fault with Hi-Z outputs

14-13EXT_WD_FREQR/W0h External watchdog frequency

0h = 10Hz

1h = 5Hz

2h = 2Hz

3h = 1Hz

12-0RESERVEDR/W0h Reserved

8.7.3.3 DEVICE_CONFIG Register (Address = A8h) [Reset = 00000000h]

DEVICE_CONFIG is shown in #HARDWARE_CONFIGURATION_HARDWARE_CONFIGURATION_HARDWARE_CONFIGURATION_DEVICE_CONFIG_FIGURE and described in #HARDWARE_CONFIGURATION_HARDWARE_CONFIGURATION_HARDWARE_CONFIGURATION_DEVICE_CONFIG_TABLE.

Return to the Summary Table.

Register to configure device

Figure 8-71 DEVICE_CONFIG Register
3130292827262524
PARITYINPUT_MAX_FREQUENCY
R/W-0hR/W-0h
2322212019181716
INPUT_MAX_FREQUENCY
R/W-0h
15141312111098
STL_ENABLESSM_CONFIGRESERVEDDEV_MODESPD_PWM_RANGE_SELECTCLK_SEL
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDEXT_CLK_ENEXT_CLK_CONFIGRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
Table 8-49 DEVICE_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-16INPUT_MAX_FREQUENCYR/W0h Maximum frequency (in Hz) for frequency based speed input
15STL_ENABLER/W0h STL enable

0h = Disable

1h = Enable

14SSM_CONFIGR/W0h SSM enable

0h = Enable

1h = Disable

13-12RESERVEDR/W0h Reserved
11DEV_MODER/W0h Device mode select

0h = Standby mode

1h = Sleep mode

10SPD_PWM_RANGE_SELECTR/W0h PWM frequency range select

0h = 325 Hz to 95 kHz speed PWM input

1h = 10 Hz to 325 Hz speed PWM input

9-8CLK_SELR/W0h Clock source

0h = Internal Oscillator

1h = N/A

2h = N/A

3h = External Clock input

7RESERVEDR/W0h Reserved
6EXT_CLK_ENR/W0h External clock enable

0h = Disable

1h = Enable

5-3EXT_CLK_CONFIGR/W0h External clock frequency

0h = 8 kHz

1h = 16 kHz

2h = 32 kHz

3h = 64 kHz

4h = 128 kHz

5h = 256 kHz

6h = 512 kHz

7h = 1024 kHz

2-0RESERVEDR/W0h Reserved