SLLSFH8B Data sheet

SLLSFH8B August 2021 – February 2022 MCT8316A

PRODUCTION DATA

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Mechanical Data (Package|Pins)

RGF|40
- MPQF173F

Thermal pad, mechanical data (Package|Pins)

RGF|40
- QFND672

Orderable Information

8.7.1 Algorithm_Configuration Registers

#ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_TABLE_1 lists the memory-mapped registers for the Algorithm_Configuration registers. All register offset addresses not listed in #ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_TABLE_1 should be considered as reserved locations and the register contents should not be modified.

Table 8-26 ALGORITHM_CONFIGURATION Registers

Address	Acronym	Register Name	Section
80h	ISD_CONFIG	ISD configuration	#ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ISD_CONFIG
82h	MOTOR_STARTUP1	Motor start-up configuration 1	#ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_MOTOR_STARTUP1
84h	MOTOR_STARTUP2	Motor start-up configuration 2	#ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_MOTOR_STARTUP2
86h	CLOSED_LOOP1	Closed loop configuration 1	#ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_CLOSED_LOOP1
88h	CLOSED_LOOP2	Closed loop configuration 2	#ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_CLOSED_LOOP2
8Ah	CLOSED_LOOP3	Closed loop configuration 3	#ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_CLOSED_LOOP3
8Ch	CLOSED_LOOP4	Closed loop configuration 4	#ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_CLOSED_LOOP4
8Eh	CONST_SPEED	Constant speed configuration	#ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_CONST_SPEED
90h	CONST_PWR	Constant power configuration	#ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_CONST_PWR
96h	150_DEG_TWO_PH_PROFILE	150° Two-ph profile	#ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_150_DEG_TWO_PH_PROFILE
98h	150_DEG_THREE_PH_PROFILE	150° Three-ph profile	#ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_150_DEG_THREE_PH_PROFILE
9Ah	TRAP_CONFIG1	Trap configuration 1	#ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_TRAP_CONFIG1
9Ch	TRAP_CONFIG2	Trap configuration 2	#ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_TRAP_CONFIG2

Complex bit access types are encoded to fit into small table cells. #ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_LEGEND shows the codes that are used for access types in this section.

Table 8-27 Algorithm_Configuration Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

8.7.1.1 ISD_CONFIG Register (Address = 80h) [Reset = 00000000h]

ISD_CONFIG is shown in #ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ISD_CONFIG_FIGURE and described in #ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ISD_CONFIG_TABLE.

Return to the Summary Table.

Figure 8-54 ISD_CONFIG Register

31	30	29	28	27	26	25	24
PARITY	ISD_EN	BRAKE_EN	HIZ_EN	RVS_DR_EN	RESYNC_EN	STAT_BRK_EN	STAT_DETECT_THR
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

23	22	21	20	19	18	17	16
STAT_DETECT_THR		BRK_MODE	BRK_CONFIG	BRK_CURR_THR			BRK_TIME
R/W-0h		R/W-0h	R/W-0h	R/W-0h			R/W-0h

15	14	13	12	11	10	9	8
BRK_TIME			HIZ_TIME				STARTUP_BRK_TIME
R/W-0h			R/W-0h				R/W-0h

7	6	5	4	3	2	1	0
STARTUP_BRK_TIME		RESYNC_MIN_THRESHOLD			RESERVED
R/W-0h		R/W-0h			R/W-0h

Table 8-28 ISD_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R/W	0h	Parity bit
30	ISD_EN	R/W	0h	ISD enable 0h = Disable 1h = Enable
29	BRAKE_EN	R/W	0h	Brake enable 0h = Disable 1h = Enable
28	HIZ_EN	R/W	0h	Hi-Z enable 0h = Disable 1h = Enable
27	RVS_DR_EN	R/W	0h	Reverse drive enable 0h = Disable 1h = Enable
26	RESYNC_EN	R/W	0h	Resynchronization enable 0h = Disable 1h = Enable
25	STAT_BRK_EN	R/W	0h	Enable or disable brake during stationary 0h = Disable 1h = Enable
24-22	STAT_DETECT_THR	R/W	0h	Stationary BEMF detect threshold 0h = 5 mV 1h = 10 mV 2h = 15 mV 3h = 20 mV 4h = 25 mV 5h = 30 mV 6h = 50 mV 7h = 100 mV
21	BRK_MODE	R/W	0h	Brake mode 0h = All three low-side FETs turned ON 1h = All three high-side FETs turned ON
20	BRK_CONFIG	R/W	0h	Brake configuration 0h = Brake time is used to come out of Brake state 1h = Brake current threshold is used to come out of Brake state
19-17	BRK_CURR_THR	R/W	0h	Brake current threshold 0h = 5 mV 1h = 10 mV 2h = 15 mV 3h = 20 mV 4h = 25 mV 5h = 30 mV 6h = 50 mV 7h = 100 mV
16-13	BRK_TIME	R/W	0h	Brake time 0h = 10 ms 1h = 50 ms 2h = 100 ms 3h = 200 ms 4h = 300 ms 5h = 400 ms 6h = 500 ms 7h = 750 ms 8h = 1 s 9h = 2 s Ah = 3 s Bh = 4 s Ch = 5 s Dh = 7.5 s Eh = 10 s Fh = 15 s
12-9	HIZ_TIME	R/W	0h	Hi-Z time 0h = 10 ms 1h = 50 ms 2h = 100 ms 3h = 200 ms 4h = 300 ms 5h = 400 ms 6h = 500 ms 7h = 750 ms 8h = 1 s 9h = 2 s Ah = 3 s Bh = 4 s Ch = 5 s Dh = 7.5 s Eh = 10 s Fh = 15 s
8-6	STARTUP_BRK_TIME	R/W	0h	Brake time when motor is stationary 0h = 1 ms 1h = 10 ms 2h = 25 ms 3h = 50 ms 4h = 100 ms 5h = 250 ms 6h = 500 ms 7h = 1000 ms
5-3	RESYNC_MIN_THRESHOLD	R/W	0h	Minimum phase BEMF below which the motor is coasted instead of resync 0h = computed based on MIN_DUTY 1h = 300 mV 2h = 400 mV 3h = 500 mV 4h = 600 mV 5h = 800 mV 6h = 1000 mV 7h = 1250 mV
2-0	RESERVED	R/W	0h	Reserved

8.7.1.2 MOTOR_STARTUP1 Register (Address = 82h) [Reset = 00000000h]

MOTOR_STARTUP1 is shown in #ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_MOTOR_STARTUP1_FIGURE and described in #ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_MOTOR_STARTUP1_TABLE.

Return to the Summary Table.

Figure 8-55 MOTOR_STARTUP1 Register

31	30	29	28	27	26	25	24
PARITY	MTR_STARTUP		ALIGN_RAMP_RATE				ALIGN_TIME
R/W-0h	R/W-0h		R/W-0h				R/W-0h

23	22	21	20	19	18	17	16
ALIGN_TIME			ALIGN_CURR_THR				IPD_CLK_FREQ
R/W-0h			R/W-0h				R/W-0h

15	14	13	12	11	10	9	8
IPD_CLK_FREQ		IPD_CURR_THR				IPD_RLS_MODE
R/W-0h		R/W-0h				R/W-0h

7	6	5	4	3	2	1	0
IPD_ADV_ANGLE		IPD_REPEAT		SLOW_FIRST_CYC_FREQ
R/W-0h		R/W-0h		R/W-0h

Table 8-29 MOTOR_STARTUP1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R/W	0h	Parity bit
30-29	MTR_STARTUP	R/W	0h	Motor start-up method 0h = Align 1h = Double Align 2h = IPD 3h = Slow first cycle
28-25	ALIGN_RAMP_RATE	R/W	0h	Align voltage ramp rate 0h = 0.1 V/s 1h = 0.2 V/s 2h = 0.5 V/s 3h = 1 V/s 4h = 2.5 V/s 5h = 5 V/s 6h = 7.5 V/s 7h = 10 V/s 8h = 25 V/s 9h = 50 V/s Ah = 75 V/s Bh = 100 V/s Ch = 250 V/s Dh = 500 V/s Eh = 750 V/s Fh = 1000 V/s
24-21	ALIGN_TIME	R/W	0h	Align time 0h = 5 ms 1h = 10 ms 2h = 25 ms 3h = 50 ms 4h = 75 ms 5h = 100 ms 6h = 200 ms 7h = 400 ms 8h = 600 ms 9h = 800 ms Ah = 1 s Bh = 2 s Ch = 4 s Dh = 6 s Eh = 8 s Fh = 10 s
20-17	ALIGN_CURR_THR	R/W	0h	Align current threshold (Align current threshold (A) = ALIGN_CURR_THR / CSA_GAIN) 0h = N/A 1h = 0.1V 2h = 0.2 V 3h = 0.3 V 4h = 0.4 V 5h = 0.5 V 6h = 0.6 V 7h = 0.7 V 8h = 0.8 V 9h = 0.9 V Ah = 1 V Bh = 1.1 V Ch = 1.2 V Dh = 1.3 V Eh = 1.4 V Fh = 1.5 V
16-14	IPD_CLK_FREQ	R/W	0h	IPD clock frequency 0h = 50 Hz 1h = 100 Hz 2h = 250 Hz 3h = 500 Hz 4h = 1000 Hz 5h = 2000 Hz 6h = 5000 Hz 7h = 10000 Hz
13-10	IPD_CURR_THR	R/W	0h	IPD current threshold (IPD current threshold (A) = IPD_CURR_THR / CSA_GAIN) 0h = N/A 1h = N/A 2h = 0.2 V 3h = 0.3 V 4h = 0.4 V 5h = 0.5 V 6h = 0.6 V 7h = 0.7 V 8h = 0.8 V 9h = 0.9 V Ah = 1 V Bh = 1.1 V Ch = 1.2 V Dh = 1.3 V Eh = 1.4 V Fh = 1.5 V
9-8	IPD_RLS_MODE	R/W	0h	IPD release mode 0h = Brake 1h = Tristate 2h = N/A 3h = N/A
7-6	IPD_ADV_ANGLE	R/W	0h	IPD advance angle 0h = 0° 1h = 30° 2h = 60° 3h = 90°
5-4	IPD_REPEAT	R/W	0h	Number of times IPD is executed 0h = one 1h = average of 2 times 2h = average of 3 times 3h = average of 4 times
3-0	SLOW_FIRST_CYC_FREQ	R/W	0h	Frequency of first cycle 0h = 0.05 Hz 1h = 0.1 Hz 2h = 0.25 Hz 3h = 0.5 Hz 4h = 1 Hz 5h = 2 Hz 6h = 3 Hz 7h = 5 Hz 8h = 10 Hz 9h = 15 Hz Bh = 25 Hz Ch = 50 Hz Dh = 100 Hz Eh = 150 Hz Fh = 200 Hz

8.7.1.3 MOTOR_STARTUP2 Register (Address = 84h) [Reset = X]

MOTOR_STARTUP2 is shown in #ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_MOTOR_STARTUP2_FIGURE and described in #ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_MOTOR_STARTUP2_TABLE.

Return to the Summary Table.

Figure 8-56 MOTOR_STARTUP2 Register

31	30	29	28	27	26	25	24
PARITY	OL_ILIMIT_CONFIG	OL_DUTY			OL_ILIMIT
R/W-0h	R/W-0h	R/W-0h			R/W-0h

23	22	21	20	19	18	17	16
OL_ILIMIT	OL_ACC_A1					OL_ACC_A2
R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
OL_ACC_A2			OPN_CL_HANDOFF_THR
R/W-0h			R/W-0h

7	6	5	4	3	2	1	0
AUTO_HANDOFF	FIRST_CYCLE_FREQ_SEL	MIN_DUTY				RESERVED
R/W-0h	R/W-0h	R/W-0h				R-X

Table 8-30 MOTOR_STARTUP2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R/W	0h	Parity bit
30	OL_ILIMIT_CONFIG	R/W	0h	Open loop current limit configuration 0h = Open loop current limit defined by OL_ILIMIT 1h = Open loop current limit defined by ILIMIT
29-27	OL_DUTY	R/W	0h	Duty cycle limit during open loop 0h = 10% 1h = 15% 2h = 20% 3h = 25% 4h = 30% 5h = 40% 6h = 50% 7h = 100%
26-23	OL_ILIMIT	R/W	0h	Open loop current limit (OL current threshold (A) = OL_CURR_THR / CSA_GAIN) 0h = N/A 1h = 0.1V 2h = 0.2 V 3h = 0.3 V 4h = 0.4 V 5h = 0.5 V 6h = 0.6 V 7h = 0.7 V 8h = 0.8 V 9h = 0.9 V Ah = 1 V Bh = 1.1 V Ch = 1.2 V Dh = 1.3 V Eh = 1.4 V Fh = 1.5 V
22-18	OL_ACC_A1	R/W	0h	Open loop acceleration A1 0h = 0.005 Hz/s 1h = 0.01 Hz/s 2h = 0.025 Hz/s 3h = 0.05 Hz/s 4h = 0.1 Hz/s 5h = 0.25 Hz/s 6h = 0.5 Hz/s 7h = 1 Hz/s 8h = 2.5 Hz/s 9h = 5 Hz/s Ah = 7.5 Hz/s Bh = 10 Hz/s Ch = 12.5 Hz/s Dh = 15 Hz/s Eh = 20 Hz/s Fh = 30 Hz/s 10h = 40 Hz/s 11h = 50 Hz/s 12h = 60 Hz/s 13h = 75 Hz/s 14h = 100 Hz/s 15h = 125 Hz/s 16h = 150 Hz/s 17h = 175 Hz/s 18h = 200 Hz/s 19h = 250 Hz/s 1Ah = 300 Hz/s 1Bh = 400 Hz/s 1Ch = 500 Hz/s 1Dh = 750 Hz/s 1Eh = 1000 Hz/s 1Fh = No Limit (32767) Hz/s
17-13	OL_ACC_A2	R/W	0h	Open loop acceleration A2 0h = 0.005 Hz/s2 1h = 0.01 Hz/s2 2h = 0.025 Hz/s2 3h = 0.05 Hz/s2 4h = 0.1 Hz/s2 5h = 0.25 Hz/s2 6h = 0.5 Hz/s2 7h = 1 Hz/s2 8h = 2.5 Hz/s2 9h = 5 Hz/s2 Ah = 7.5 Hz/s2 Bh = 10 Hz/s2 Ch = 12.5 Hz/s2 Dh = 15 Hz/s2 Eh = 20 Hz/s2 Fh = 30 Hz/s2 10h = 40 Hz/s2 11h = 50 Hz/s2 12h = 60 Hz/s2 13h = 75 Hz/s2 14h = 100 Hz/s2 15h = 125 Hz/s2 16h = 150 Hz/s2 17h = 175 Hz/s2 18h = 200 Hz/s2 19h = 250 Hz/s2 1Ah = 300 Hz/s2 1Bh = 400 Hz/s2 1Ch = 500 Hz/s2 1Dh = 750 Hz/s2 1Eh = 1000 Hz/s2 1Fh = No Limit (32767) Hz/s2
12-8	OPN_CL_HANDOFF_THR	R/W	0h	Open to closed loop handoff threshold 0h = 1 Hz 1h = 4 Hz 2h = 8 Hz 3h = 12 Hz 4h = 16 Hz 5h = 20 Hz 6h = 24 Hz 7h = 28 Hz 8h = 32 Hz 9h = 36 Hz Ah = 40 Hz Bh = 45 Hz Ch = 50 Hz Dh = 55 Hz Eh = 60 Hz Fh = 65 Hz 10h = 70 Hz 11h = 75 Hz 12h = 80 Hz 13h = 85 Hz 14h = 90 Hz 15h = 100 Hz 16h = 150 Hz 17h = 200 Hz 18h = 250 Hz 19h = 300 Hz 1Ah = 350 Hz 1Bh = 400 Hz 1Ch = 450 Hz 1Dh = 500 Hz 1Eh = 550 Hz 1Fh = 600 Hz
7	AUTO_HANDOFF	R/W	0h	Auto handoff enable 0h = Disable Auto Handoff (and use OPN_CL_HANDOFF_THR) 1h = Enable Auto Handoff
6	FIRST_CYCLE_FREQ_SEL	R/W	0h	First cycle frequency select 0h = Defined by SLOW_FIRST_CYC_FREQ 1h = 0 Hz
5-2	MIN_DUTY	R/W	0h	Min operational duty cycle 0h = 1.5 % 1h = 2 % 2h = 3 % 3h = 4 % 4h = 5 % 5h = 6 % 6h = 7 % 7h = 8 % 8h = 9 % 9h = 10 % Ah = 12 % Bh = 15 % Ch = 17.5 % Dh = 20 % Eh = 25 % Fh = 30 %
1-0	RESERVED	R	X	Reserved

8.7.1.4 CLOSED_LOOP1 Register (Address = 86h) [Reset = 00000000h]

CLOSED_LOOP1 is shown in #ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_CLOSED_LOOP1_FIGURE and described in #ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_CLOSED_LOOP1_TABLE.

Return to the Summary Table.

Figure 8-57 CLOSED_LOOP1 Register

31	30	29	28	27	26	25	24
PARITY	COMM_CONTROL		CL_ACC
R/W-0h	R/W-0h		R/W-0h

23	22	21	20	19	18	17	16
CL_DEC_CONFIG	CL_DEC					PWM_FREQ_OUT
R/W-0h	R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
PWM_FREQ_OUT			PWM_MODUL		PWM_MODE	LD_ANGLE_POLARITY	LD_ANGLE
R/W-0h			R/W-0h		R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
LD_ANGLE							RESERVED
R/W-0h							R/W-0h

Table 8-31 CLOSED_LOOP1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R/W	0h	Parity bit
30-29	COMM_CONTROL	R/W	0h	Trapezoidal commutation mode 0h = 120° Commutation 1h = Variable commutation between 120° and 150° 2h = N/A 3h = N/A
28-24	CL_ACC	R/W	0h	Closed loop acceleration rate 0h = 0.005 V/s 1h = 0.01 V/s 2h = 0.025 V/s 3h = 0.05 V/s 4h = 0.1 V/s 5h = 0.25 V/s 6h = 0.5 V/s 7h = 1 V/s 8h = 2.5 V/s 9h = 5 V/s Ah = 7.5 V/s Bh = 10 V/s Ch = 12.5 V/s Dh = 15 V/s Eh = 20 V/s Fh = 30 V/s 10h = 40 V/s 11h = 50 V/s 12h = 60 V/s 13h = 75 V/s 14h = 100 V/s 15h = 125 V/s 16h = 150 V/s 17h = 175 V/s 18h = 200 V/s 19h = 250 V/s 1Ah = 300 V/s 1Bh = 400 V/s 1Ch = 500 V/s 1Dh = 750 V/s 1Eh = 1000 V/s 1Fh = 32767 V/s
23	CL_DEC_CONFIG	R/W	0h	Closed loop decel configuration 0h = Close loop deceleration defined by CL_DEC 1h = Close loop deceleration defined by CL_ACC
22-18	CL_DEC	R/W	0h	Closed loop deceleration rate 0h = 0.005 V/s 1h = 0.01 V/s 2h = 0.025 V/s 3h = 0.05 V/s 4h = 0.1 V/s 5h = 0.25 V/s 6h = 0.5 V/s 7h = 1 V/s 8h = 2.5 V/s 9h = 5 V/s Ah = 7.5 V/s Bh = 10 V/s Ch = 12.5 V/s Dh = 15 V/s Eh = 20 V/s Fh = 30 V/s 10h = 40 V/s 11h = 50 V/s 12h = 60 V/s 13h = 75 V/s 14h = 100 V/s 15h = 125 V/s 16h = 150 V/s 17h = 175 V/s 18h = 200 V/s 19h = 250 V/s 1Ah = 300 V/s 1Bh = 400 V/s 1Ch = 500 V/s 1Dh = 750 V/s 1Eh = 1000 V/s 1Fh = 32767 V/s
17-13	PWM_FREQ_OUT	R/W	0h	Output PWM switching frequency 0h = 5 kHz 1h = 6 kHz 2h = 7 kHz 3h = 8 kHz 4h = 9 kHz 5h = 10 kHz 6h = 11 kHz 7h = 12 kHz 8h = 13 kHz 9h = 14 kHz Ah = 15 kHz Bh = 16 kHz Ch = 17 kHz Dh = 18 kHz Eh = 19 kHz Fh = 20 kHz 10h = 25 kHz 11h = 30 kHz 12h = 35 kHz 13h = 40 kHz 14h = 45 kHz 15h = 50 kHz 16h = 55 kHz 17h = 60 kHz 18h = 65 kHz 19h = 70 kHz 1Ah = 75 kHz 1Bh = 80 kHz 1Ch = 85 kHz 1Dh = 90 kHz 1Eh = 95 kHz 1Fh = 100 kHz
12-11	PWM_MODUL	R/W	0h	PWM modulation. 0h = High-Side Modulation 1h = Low-Side Modulation 2h = Mixed Modulation 3h = N/A
10	PWM_MODE	R/W	0h	PWM mode 0h = Single Ended Mode 1h = Complementary Mode
9	LD_ANGLE_POLARITY	R/W	0h	Polarity of applied lead angle 0h = Negative 1h = Positive
8-1	LD_ANGLE	R/W	0h	Lead Angle {Lead Angle (deg) = LD_ANGLE * 0.12}
0	RESERVED	R/W	0h	Reserved

8.7.1.5 CLOSED_LOOP2 Register (Address = 88h) [Reset = 00000000h]

CLOSED_LOOP2 is shown in #ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_CLOSED_LOOP2_FIGURE and described in #ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_CLOSED_LOOP2_TABLE.

Return to the Summary Table.

Figure 8-58 CLOSED_LOOP2 Register

31	30	29	28	27	26	25	24
PARITY	FG_SEL		FG_DIV_FACTOR				FG_CONFIG
R/W-0h	R/W-0h		R/W-0h				R/W-0h

23	22	21	20	19	18	17	16
FG_BEMF_THR			MTR_STOP			MTR_STOP_BRK_TIME
R/W-0h			R/W-0h			R/W-0h

15	14	13	12	11	10	9	8
MTR_STOP_BRK_TIME		ACT_SPIN_BRK_THR			BRAKE_DUTY_THRESHOLD
R/W-0h		R/W-0h			R/W-0h

7	6	5	4	3	2	1	0
AVS_EN	CBC_ILIMIT				RESERVED
R/W-0h	R/W-0h				R/W-0h

Table 8-32 CLOSED_LOOP2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R/W	0h	Parity bit
30-29	FG_SEL	R/W	0h	FG mode select 0h = Output FG in open loop and closed loop 1h = Output FG in only closed loop 2h = Output FG in open loop for the first try. 3h = N/A
28-25	FG_DIV_FACTOR	R/W	0h	FG division factor 0h = Divide by 3 (2-pole motor mechanical speed/3) 1h = Divide by 1 (2-pole motor mechanical speed) 2h = Divide by 2 (4-pole motor mechanical speed) 3h = Divide by 3 (6-pole motor mechanical speed) 4h = Divide by 4 (8-pole motor mechanical speed) 5h = Divide by 5 (10-pole motor mechanical speed) 6h = Divide by 6 (12-pole motor mechanical speed) 7h = Divide by 7 (14-pole motor mechanical speed) 8h = Divide by 8 (16-pole motor mechanical speed) 9h = Divide by 9 (18-pole motor mechanical speed) Ah = Divide by 10 (20-pole motor mechanical speed) Bh = Divide by 11 (22-pole motor mechanical speed) Ch = Divide by 12 (24-pole motor mechanical speed) Dh = Divide by 13 (26-pole motor mechanical speed) Eh = Divide by 14 (28-pole motor mechanical speed) Fh = Divide by 15 (30-pole motor mechanical speed)
24	FG_CONFIG	R/W	0h	FG output configuration 0h = FG active till speed drops below BEMF threshold defined by FG_BEMF_THR 1h = FG active as long as motor is driven
23-21	FG_BEMF_THR	R/W	0h	FG output BEMF threshold 0h = +/- 1mV 1h = +/- 2mV 2h = +/- 5mV 3h = +/- 10mV 4h = +/- 20mV 5h = +/- 30mV 6h = N/A 7h = N/A
20-18	MTR_STOP	R/W	0h	Motor stop method 0h = Hi-z 1h = Recirculation 2h = Low-side braking 3h = High-side braking 4h = Active spin down 5h = N/A 6h = N/A 7h = N/A
17-14	MTR_STOP_BRK_TIME	R/W	0h	Brake time during motor stop 0h = 1 ms 1h = 2 ms 2h = 5 ms 3h = 10 ms 4h = 15 ms 5h = 25 ms 6h = 50 ms 7h = 75 ms 8h = 100 ms 9h = 250 ms Ah = 500 ms Bh = 1000 ms Ch = 2500 ms Dh = 5000 ms Eh = 10000 ms Fh = 15000 ms
13-11	ACT_SPIN_BRK_THR	R/W	0h	Duty cycle threshold for motor stop using active spin down, low- and high-side braking 0h = Immediate 1h = 50 % 2h = 25 % 3h = 15 % 4h = 10 % 5h = 7.5 % 6h = 5 % 7h = 2.5 %
10-8	BRAKE_DUTY_THRESHOLD	R/W	0h	Duty cycle threshold for BRAKE pin based low-side braking 0h = Immediate 1h = 50 % 2h = 25 % 3h = 15 % 4h = 10 % 5h = 7.5 % 6h = 5 % 7h = 2.5 %
7	AVS_EN	R/W	0h	AVS enable 0h = Disable 1h = Enable
6-3	CBC_ILIMIT	R/W	0h	Cycle by Cycle (CBC) current limit (CBC current limit (A) = CBC_ILIMIT / CSA_GAIN) 0h = N/A 1h = 0.1 V 2h = 0.2 V 3h = 0.3 V 4h = 0.4 V 5h = 0.5 V 6h = 0.6 V 7h = 0.7 V 8h = 0.8 V 9h = 0.9 V Ah = 1 V Bh = 1.1 V Ch = 1.2 V Dh = 1.3 V Eh = 1.4 V Fh = 1.5 V
2-0	RESERVED	R/W	0h	Reserved

8.7.1.6 CLOSED_LOOP3 Register (Address = 8Ah) [Reset = 14000000h]

CLOSED_LOOP3 is shown in #ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_CLOSED_LOOP3_FIGURE and described in #ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_CLOSED_LOOP3_TABLE.

Return to the Summary Table.

Figure 8-59 CLOSED_LOOP3 Register

31	30	29	28	27	26	25	24
PARITY	DYN_DGS_FILT_COUNT		DYN_DGS_UPPER_LIM		DYN_DGS_LOWER_LIM		INTEG_CYCL_THR_LOW
R/W-0h	R/W-0h		R/W-2h		R/W-2h		R/W-0h

23	22	21	20	19	18	17	16
INTEG_CYCL_THR_LOW	INTEG_CYCL_THR_HIGH		INTEG_DUTY_THR_LOW		INTEG_DUTY_THR_HIGH		BEMF_THRESHOLD2
R/W-0h	R/W-0h		R/W-0h		R/W-0h		R/W-0h

15	14	13	12	11	10	9	8
BEMF_THRESHOLD2					BEMF_THRESHOLD1
R/W-0h					R/W-0h

7	6	5	4	3	2	1	0
BEMF_THRESHOLD1			INTEG_ZC_METHOD	DEGAUSS_MAX_WIN			DYN_DEGAUSS_EN
R/W-0h			R/W-0h	R/W-0h			R/W-0h

Table 8-33 CLOSED_LOOP3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R/W	0h	Parity bit
30-29	DYN_DGS_FILT_COUNT	R/W	0h	Number of samples needed for dynamic degauss check 0h = 2 1h = 3 2h = 4 3h = 5
28-27	DYN_DGS_UPPER_LIM	R/W	2h	Dynamic degauss voltage upper bound 0h = (VM - 0.09) V 1h = (VM - 0.12) V 2h = (VM - 0.15) V 3h = (VM - 0.18) V
26-25	DYN_DGS_LOWER_LIM	R/W	2h	Dynamic degauss voltage lower bound 0h = 0.03 V 1h = 0.06 V 2h = 0.09 V 3h = 0.12 V
24-23	INTEG_CYCL_THR_LOW	R/W	0h	Number of BEMF samples per 30° below which commutation method switches from integration to ZC 0h = 3 1h = 4 2h = 6 3h = 8
22-21	INTEG_CYCL_THR_HIGH	R/W	0h	Number of BEMF samples per 30° above which commutation method switches from ZC to integration 0h = 4 1h = 6 2h = 8 3h = 10
20-19	INTEG_DUTY_THR_LOW	R/W	0h	Duty cycle below which commutation method switches from integration to ZC 0h = 12 % 1h = 15 % 2h = 18 % 3h = 20 %
18-17	INTEG_DUTY_THR_HIGH	R/W	0h	Duty cycle above which commutation method switches from ZC to integration 0h = 12 % 1h = 15 % 2h = 18 % 3h = 20 %
16-11	BEMF_THRESHOLD2	R/W	0h	BEMF threshold for integration based commutation during falling floating phase voltage 0h = 0 1h = 25 2h = 50 3h = 75 4h = 100 5h = 125 6h = 150 7h = 175 8h = 200 9h = 225 Ah = 250 Bh = 275 Ch = 300 Dh = 325 Eh = 350 Fh = 375 10h = 400 11h = 425 12h = 450 13h = 475 14h = 500 15h = 525 16h = 550 17h = 575 18h = 600 19h = 625 1Ah = 650 1Bh = 675 1Ch = 700 1Dh = 725 1Eh = 750 1Fh = 775 20h = 800 21h = 850 22h = 900 23h = 950 24h = 1000 25h = 1050 26h = 1100 27h = 1150 28h = 1200 29h = 1250 2Ah = 1300 2Bh = 1350 2Ch = 1400 2Dh = 1450 2Eh = 1500 2Fh = 1550 30h = 1600 31h = 1700 32h = 1800 33h = 1900 34h = 2000 35h = 2100 36h = 2200 37h = 2300 38h = 2400 39h = 2600 3Ah = 2800 3Bh = 3000 3Ch = 3200 3Dh = 3400 3Eh = 3600 3Fh = 3800
10-5	BEMF_THRESHOLD1	R/W	0h	BEMF threshold for integration based commutation during rising floating phase voltage 0h = 0 1h = 25 2h = 50 3h = 75 4h = 100 5h = 125 6h = 150 7h = 175 8h = 200 9h = 225 Ah = 250 Bh = 275 Ch = 300 Dh = 325 Eh = 350 Fh = 375 10h = 400 11h = 425 12h = 450 13h = 475 14h = 500 15h = 525 16h = 550 17h = 575 18h = 600 19h = 625 1Ah = 650 1Bh = 675 1Ch = 700 1Dh = 725 1Eh = 750 1Fh = 775 20h = 800 21h = 850 22h = 900 23h = 950 24h = 1000 25h = 1050 26h = 1100 27h = 1150 28h = 1200 29h = 1250 2Ah = 1300 2Bh = 1350 2Ch = 1400 2Dh = 1450 2Eh = 1500 2Fh = 1550 30h = 1600 31h = 1700 32h = 1800 33h = 1900 34h = 2000 35h = 2100 36h = 2200 37h = 2300 38h = 2400 39h = 2600 3Ah = 2800 3Bh = 3000 3Ch = 3200 3Dh = 3400 3Eh = 3600 3Fh = 3800
4	INTEG_ZC_METHOD	R/W	0h	Commutation method select 0h = ZC based 1h = Integration based
3-1	DEGAUSS_MAX_WIN	R/W	0h	Maximum degauss window 0h = 22.5° 1h = 10° 2h = 15° 3h = 18° 4h = 30° 5h = 37.5° 6h = 45° 7h = 60°
0	DYN_DEGAUSS_EN	R/W	0h	Dynamic degauss detection 0h = Disable 1h = Enable

8.7.1.7 CLOSED_LOOP4 Register (Address = 8Ch) [Reset = 00000000h]

CLOSED_LOOP4 is shown in #ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_CLOSED_LOOP4_FIGURE and described in #ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_CLOSED_LOOP4_TABLE.

Return to the Summary Table.

Figure 8-60 CLOSED_LOOP4 Register

31	30	29	28	27	26	25	24
PARITY	RESERVED
R/W-0h	R/W-0h

23	22	21	20	19	18	17	16
RESERVED				WCOMP_BLANK_EN	FAST_DEC_DUTY_WIN
R/W-0h				R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
FAST_DEC_DUTY_THR			DYN_BRK_CURR_LOW_LIM				DYNAMIC_BRK_CURR
R/W-0h			R/W-0h				R/W-0h

7	6	5	4	3	2	1	0
FAST_DECEL_EN	FAST_DECEL_CURR_LIM				FAST_BRK_DELTA
R/W-0h	R/W-0h				R/W-0h

Table 8-34 CLOSED_LOOP4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R/W	0h	Parity bit
30-20	RESERVED	R/W	0h	Reserved
19	WCOMP_BLANK_EN	R/W	0h	Enable WCOMP blanking during fast deceleration 0h = Disable 1h = Enable
18-16	FAST_DEC_DUTY_WIN	R/W	0h	Fast deceleration duty window 0h = 0 % 1h = 2.5 % 2h = 5 % 3h = 7.5 % 4h = 10 % 5h = 15 % 6h = 20 % 7h = 25 %
15-13	FAST_DEC_DUTY_THR	R/W	0h	Fast deceleration duty threshold 0h = 100 % 1h = 95 % 2h = 90 % 3h = 85 % 4h = 80 % 5h = 75 % 6h = 70% 7h = 65 %
12-9	DYN_BRK_CURR_LOW_LIM	R/W	0h	Fast deceleration dynamic current limit lower threshold (Deceleration current lower threshold (A) = DYN_BRK_CURR_LOW_LIM / CSA_GAIN) 0h = N/A 1h = 0.1V 2h = 0.2 V 3h = 0.3 V 4h = 0.4 V 5h = 0.5 V 6h = 0.6 V 7h = 0.7 V 8h = 0.8 V 9h = 0.9 V Ah = 1 V Bh = 1.1 V Ch = 1.2 V Dh = 1.3 V Eh = 1.4 V Fh = 1.5 V
8	DYNAMIC_BRK_CURR	R/W	0h	Enable dynamic decrease in current limit during fast deceleration 0h = Disable 1h = Enable
7	FAST_DECEL_EN	R/W	0h	Fast deceleration enable 0h = Disable 1h = Enable
6-3	FAST_DECEL_CURR_LIM	R/W	0h	Deceleration current threshold (Fast Deceleration current limit upper threshold (A) = FAST_DECEL_CURR_LIM / CSA_GAIN) 0h = N/A 1h = 0.1V 2h = 0.2 V 3h = 0.3 V 4h = 0.4 V 5h = 0.5 V 6h = 0.6 V 7h = 0.7 V 8h = 0.8 V 9h = 0.9 V Ah = 1 V Bh = 1.1 V Ch = 1.2 V Dh = 1.3 V Eh = 1.4 V Fh = 1.5 V
2-0	FAST_BRK_DELTA	R/W	0h	Fast deceleration exit speed delta 0h = 0.5 % 1h = 1 % 2h = 1.5 % 3h = 2 % 4h = 2.5 % 5h = 3 % 6h = 4 % 7h = 5 %

8.7.1.8 CONST_SPEED Register (Address = 8Eh) [Reset = 00000000h]

CONST_SPEED is shown in #ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_CONST_SPEED_FIGURE and described in #ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_CONST_SPEED_TABLE.

Return to the Summary Table.

Figure 8-61 CONST_SPEED Register

31	30	29	28	27	26	25	24
PARITY	RESERVED	SPD_POWER_KP
R/W-0h	R/W-0h	R/W-0h

23	22	21	20	19	18	17	16
SPD_POWER_KP				SPD_POWER_KI
R/W-0h				R/W-0h

15	14	13	12	11	10	9	8
SPD_POWER_KI
R/W-0h

7	6	5	4	3	2	1	0
SPD_POWER_V_MAX			SPD_POWER_V_MIN			CLOSED_LOOP_MODE
R/W-0h			R/W-0h			R/W-0h

Table 8-35 CONST_SPEED Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R/W	0h	Parity bit
30	RESERVED	R/W	0h	Reserved
29-20	SPD_POWER_KP	R/W	0h	Speed/ Power loop Kp (Kp = SPD_LOOP_KP / 10000)
19-8	SPD_POWER_KI	R/W	0h	Speed/ Power loop Ki (Ki = SPD_LOOP_KI / 1000000)
7-5	SPD_POWER_V_MAX	R/W	0h	Upper saturation limit for speed/ power loop 0h = 100 % 1h = 95 % 2h = 90 % 3h = 85 % 4h = 80 % 5h = 75 % 6h = 70% 7h = 65 %
4-2	SPD_POWER_V_MIN	R/W	0h	Lower saturation limit for speed/power loop 0h = 0 % 1h = 2.5 % 2h = 5 % 3h = 7.5 % 4h = 10 % 5h = 15 % 6h = 20 % 7h = 25 %
1-0	CLOSED_LOOP_MODE	R/W	0h	Closed loop mode 0h = Disabled 1h = Speed Loop 2h = Power Loop 3h = Reserved

8.7.1.9 CONST_PWR Register (Address = 90h) [Reset = 00000000h]

CONST_PWR is shown in #ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_CONST_PWR_FIGURE and described in #ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_CONST_PWR_TABLE.

Return to the Summary Table.

Figure 8-62 CONST_PWR Register

31	30	29	28	27	26	25	24
PARITY	MAX_SPEED
R/W-0h	R/W-0h

23	22	21	20	19	18	17	16
MAX_SPEED
R/W-0h

15	14	13	12	11	10	9	8
MAX_SPEED	DEADTIME_COMP_EN	MAX_POWER
R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
MAX_POWER				CONST_POWER_LIMIT_HYST		CONST_POWER_MODE
R/W-0h				R/W-0h		R/W-0h

Table 8-36 CONST_PWR Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R/W	0h	Parity bit
30-15	MAX_SPEED	R/W	0h	Maximum Speed (Maximum Speed (Hz) = MAX_SPEED / 16)
14	DEADTIME_COMP_EN	R/W	0h	Enable dead time compensation 0h = Disable 1h = Enable
13-4	MAX_POWER	R/W	0h	Maximum power (Maximum power (W) = MAX_POWER / 4)
3-2	CONST_POWER_LIMIT_HYST	R/W	0h	Hysteresis for input power regulation 0h = 5 % 1h = 7.5 % 2h = 10 % 3h = 12.5 %
1-0	CONST_POWER_MODE	R/W	0h	Input power regulation mode 0h = Disabled 1h = Closed Loop Power Control 2h = Power Limit Control 3h = Reserved

8.7.1.10 150_DEG_TWO_PH_PROFILE Register (Address = 96h) [Reset = 00000000h]

150_DEG_TWO_PH_PROFILE is shown in #ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_150_DEG_TWO_PH_PROFILE_FIGURE and described in #ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_150_DEG_TWO_PH_PROFILE_TABLE.

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Figure 8-63 150_DEG_TWO_PH_PROFILE Register

31	30	29	28	27	26	25	24
PARITY	TWOPH_STEP0			TWOPH_STEP1			TWOPH_STEP2
R/W-0h	R/W-0h			R/W-0h			R/W-0h

23	22	21	20	19	18	17	16
TWOPH_STEP2		TWOPH_STEP3			TWOPH_STEP4
R/W-0h		R/W-0h			R/W-0h

15	14	13	12	11	10	9	8
TWOPH_STEP5			TWOPH_STEP6			TWOPH_STEP7
R/W-0h			R/W-0h			R/W-0h

7	6	5	4	3	2	1	0
TWOPH_STEP7	RESERVED
R/W-0h	R/W-0h

Table 8-37 150_DEG_TWO_PH_PROFILE Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R/W	0h	Parity bit
30-28	TWOPH_STEP0	R/W	0h	150° modulation , Two ph. - step duty - 0 0h = 0% 1h = 50 % 2h = 75 % 3h = 83.75 % 4h = 87.5 % 5h = 93.75 % 6h = 97.5 % 7h = 99 %
27-25	TWOPH_STEP1	R/W	0h	150° modulation , Two ph. - step duty - 1 0h = 0% 1h = 50 % 2h = 75 % 3h = 83.75 % 4h = 87.5 % 5h = 93.75 % 6h = 97.5 % 7h = 99 %
24-22	TWOPH_STEP2	R/W	0h	150° modulation, Two ph. - step duty - 2 0h = 0% 1h = 50 % 2h = 75 % 3h = 83.75 % 4h = 87.5 % 5h = 93.75 % 6h = 97.5 % 7h = 99 %
21-19	TWOPH_STEP3	R/W	0h	150° modulation, Two ph. - step duty - 3 0h = 0% 1h = 50 % 2h = 75 % 3h = 83.75 % 4h = 87.5 % 5h = 93.75 % 6h = 97.5 % 7h = 99 %
18-16	TWOPH_STEP4	R/W	0h	150° modulation, Two ph. - step duty - 4 0h = 0% 1h = 50 % 2h = 75 % 3h = 83.75 % 4h = 87.5 % 5h = 93.75 % 6h = 97.5 % 7h = 99 %
15-13	TWOPH_STEP5	R/W	0h	150° modulation, Two ph. - step duty - 5 0h = 0% 1h = 50 % 2h = 75 % 3h = 83.75 % 4h = 87.5 % 5h = 93.75 % 6h = 97.5 % 7h = 99 %
12-10	TWOPH_STEP6	R/W	0h	150° modulation, Two ph. - step duty - 6 0h = 0% 1h = 50 % 2h = 75 % 3h = 83.75 % 4h = 87.5 % 5h = 93.75 % 6h = 97.5 % 7h = 99 %
9-7	TWOPH_STEP7	R/W	0h	150° modulation, Two ph. - step duty - 7 0h = 0% 1h = 50 % 2h = 75 % 3h = 83.75 % 4h = 87.5 % 5h = 93.75 % 6h = 97.5 % 7h = 99 %
6-0	RESERVED	R/W	0h	reserved bits for algo parameter update

8.7.1.11 150_DEG_THREE_PH_PROFILE Register (Address = 98h) [Reset = 00000000h]

150_DEG_THREE_PH_PROFILE is shown in #ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_150_DEG_THREE_PH_PROFILE_FIGURE and described in #ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_150_DEG_THREE_PH_PROFILE_TABLE.

Return to the Summary Table.

Figure 8-64 150_DEG_THREE_PH_PROFILE Register

31	30	29	28	27	26	25	24
PARITY	THREEPH_STEP0			THREEPH_STEP1			THREEPH_STEP2
R/W-0h	R/W-0h			R/W-0h			R/W-0h

23	22	21	20	19	18	17	16
THREEPH_STEP2		THREEPH_STEP3			THREEPH_STEP4
R/W-0h		R/W-0h			R/W-0h

15	14	13	12	11	10	9	8
THREEPH_STEP5			THREEPH_STEP6			THREEPH_STEP7
R/W-0h			R/W-0h			R/W-0h

7	6	5	4	3	2	1	0
THREEPH_STEP7	LEAD_ANGLE_150DEG_ADV		RESERVED
R/W-0h	R/W-0h		R/W-0h

Table 8-38 150_DEG_THREE_PH_PROFILE Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R/W	0h	Parity bit
30-28	THREEPH_STEP0	R/W	0h	150° modulation, Three ph. - step duty - 0 0h = 0% 1h = 50 % 2h = 75 % 3h = 83.75 % 4h = 87.5 % 5h = 93.75 % 6h = 97.5 % 7h = 99 %
27-25	THREEPH_STEP1	R/W	0h	150° modulation, Three ph. - step duty - 1 0h = 0% 1h = 50 % 2h = 75 % 3h = 83.75 % 4h = 87.5 % 5h = 93.75 % 6h = 97.5 % 7h = 99 %
24-22	THREEPH_STEP2	R/W	0h	150° modulation, Three ph. - step duty - 2 0h = 0% 1h = 50 % 2h = 75 % 3h = 83.75 % 4h = 87.5 % 5h = 93.75 % 6h = 97.5 % 7h = 99 %
21-19	THREEPH_STEP3	R/W	0h	150° modulation, Three ph. - step duty - 3 0h = 0% 1h = 50 % 2h = 75 % 3h = 83.75 % 4h = 87.5 % 5h = 93.75 % 6h = 97.5 % 7h = 99 %
18-16	THREEPH_STEP4	R/W	0h	150° modulation, Three ph. - step duty - 4 0h = 0.0 % 1h = 0.5 % 2h = 0.75 % 3h = 0.8375 % 4h = 0.875 % 5h = 0.9375 % 6h = 0.975 % 7h = 0.99 %
15-13	THREEPH_STEP5	R/W	0h	150° modulation, Three ph. - step duty - 5 0h = 0% 1h = 50 % 2h = 75 % 3h = 83.75 % 4h = 87.5 % 5h = 93.75 % 6h = 97.5 % 7h = 99 %
12-10	THREEPH_STEP6	R/W	0h	150° modulation, Three ph. - step duty - 6 0h = 0% 1h = 50 % 2h = 75 % 3h = 83.75 % 4h = 87.5 % 5h = 93.75 % 6h = 97.5 % 7h = 99 %
9-7	THREEPH_STEP7	R/W	0h	150° modulation, Three ph. - step duty - 7 0h = 0% 1h = 50 % 2h = 75 % 3h = 83.75 % 4h = 87.5 % 5h = 93.75 % 6h = 97.5 % 7h = 99 %
6-5	LEAD_ANGLE_150DEG_ADV	R/W	0h	Angle advance for 150° modulation 0h = 0° 1h = 5° 2h = 10° 3h = 15°
4-0	RESERVED	R/W	0h	Reserved

8.7.1.12 TRAP_CONFIG1 Register (Address = 9Ah) [Reset = 00000000h]

TRAP_CONFIG1 is shown in #ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_TRAP_CONFIG1_FIGURE and described in #ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_TRAP_CONFIG1_TABLE.

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Figure 8-65 TRAP_CONFIG1 Register

31	30	29	28	27	26	25	24
PARITY	RESERVED		RESERVED			RESERVED
R/W-0h	R/W-0h		R/W-0h			R/W-0h

23	22	21	20	19	18	17	16
OL_HANDOFF_CYCLES		RESERVED			AVS_NEG_CURR_LIMIT
R/W-0h		R/W-0h			R/W-0h

15	14	13	12	11	10	9	8
AVS_LIMIT_HYST	ISD_BEMF_THR					ISD_CYCLE_THR
R/W-0h	R/W-0h					R/W-0h

7	6	5	4	3	2	1	0
ISD_CYCLE_THR	RESERVED	RESERVED		ZC_ANGLE_OL_THR		FAST_STARTUP_DIV_FACTOR
R/W-0h	R/W-0h	R/W-0h		R/W-0h		R/W-0h

Table 8-39 TRAP_CONFIG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R/W	0h	Parity bit
30-29	RESERVED	R/W	0h	Reserved
28-26	RESERVED	R/W	0h	Reserved
25-24	RESERVED	R/W	0h	Reserved
23-22	OL_HANDOFF_CYCLES	R/W	0h	Open loop handoff cycles 0h = 3 1h = 6 2h = 12 3h = 24
21-19	RESERVED	R/W	0h	Reserved
18-16	AVS_NEG_CURR_LIMIT	R/W	0h	AVS negative current limit (AVS negative current limit (A) = (AVS_NEG_CURRENT_LIMIT * 3 /4095) / CSA_GAIN) 0h = 0 1h = -40 2h = -30 3h = -20 4h = -10 5h = 10 6h = 20 7h = 30
15	AVS_LIMIT_HYST	R/W	0h	AVS current hysteresis (AVS positive current limit (A) = ((AVS_LIMIT_HYST + AVS_NEG_CURR_LIMIT) * 3 /4095) / CSA_GAIN) 0h = 20 1h = 10
14-10	ISD_BEMF_THR	R/W	0h	ISD BEMF threshold (ISD BEMF threshold = 200 * ISD_BEMF_THR) 0h = 0 1h = 200 2h = 400 3h = 600 4h = 800 5h = 1000 6h = 1200 7h = 1400 8h = 1600 9h = 1800 Ah = 2000 Bh = 2200 Ch = 2400 Dh = 2600 Eh = 2800 Fh = 3000 10h = 3200 11h = 3400 12h = 3600 13h = 3800 14h = 4000 15h = 4200 16h = 4400 17h = 4600 18h = 4800 19h = 5000 1Ah = 5200 1Bh = 5400 1Ch = 5600 1Dh = 5800 1Eh = 6000 1Fh = 6200
9-7	ISD_CYCLE_THR	R/W	0h	ISD cycle threshold 0h = 2, 1h = 5, 2h = 8, 3h = 11, 4h = 14, 5h = 17, 6h = 20, 7h = 23
6	RESERVED	R/W	0h	Reserved
5-4	RESERVED	R/W	0h	Reserved
3-2	ZC_ANGLE_OL_THR	R/W	0h	Angle above which the ZC detection is done during OL 0h = 5° 1h = 8° 2h = 12° 3h = 15°
1-0	FAST_STARTUP_DIV_FACTOR	R/W	0h	Dynamic A1, A2 change rate 0h = 1 1h = 2 2h = 4 3h = 8

8.7.1.13 TRAP_CONFIG2 Register (Address = 9Ch) [Reset = 00200000h]

TRAP_CONFIG2 is shown in #ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_TRAP_CONFIG2_FIGURE and described in #ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_TRAP_CONFIG2_TABLE.

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Figure 8-66 TRAP_CONFIG2 Register

31	30	29	28	27	26	25	24
PARITY	TBLANK				TPWDTH
R/W-0h	R/W-0h				R/W-0h

23	22	21	20	19	18	17	16
RESERVED	RESERVED	RESERVED	ALIGN_DUTY			RESERVED
R/W-0h	R/W-0h	R/W-1h	R/W-0h			R/W-0h

15	14	13	12	11	10	9	8
RESERVED
R/W-0h

7	6	5	4	3	2	1	0
RESERVED
R/W-0h

Table 8-40 TRAP_CONFIG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R/W	0h	Parity bit
30-27	TBLANK	R/W	0h	Blanking time after PWM edge 0h = 0 µs 1h = 1 µs 2h = 2 µs 3h = 3 µs 4h = 4 µs 5h = 5 µs 6h = 6 µs 7h = 7 µs 8h = 8 µs 9h = 9 µs Ah = 10 µs Bh = 11 µs Ch = 12 µs Dh = 13 µs Eh = 14 µs Fh = 15 µs
26-24	TPWDTH	R/W	0h	Comparator deglitch time 0h = 0 µs 1h = 1 µs 2h = 2 µs 3h = 3 µs 4h = 4 µs 5h = 5 µs 6h = 6 µs 7h = 7 µs
23	RESERVED	R/W	0h	Reserved
22	RESERVED	R/W	0h	Reserved
21	RESERVED	R/W	1h	Reserved
20-18	ALIGN_DUTY	R/W	0h	Duty cycle limit during align 0h = 10 % 1h = 15 % 2h = 20 % 3h = 25 % 4h = 30 % 5h = 40 % 6h = 50 % 7h = 100 %
17-0	RESERVED	R/W	0h	Reserved