SLLSFH8A August   2021  – December 2021 MCT8316A

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Output Stage
      2. 8.3.2  Device Interface Modes
        1. 8.3.2.1 Interface - Control and Monitoring
        2. 8.3.2.2 I2C Interface
        3. 8.3.2.3 Hardware Interface - Pin Configuration
      3. 8.3.3  Step-Down Mixed-Mode Buck Regulator
        1. 8.3.3.1 Buck in Inductor Mode
        2. 8.3.3.2 Buck in Resistor mode
        3. 8.3.3.3 Buck Regulator with External LDO
        4. 8.3.3.4 AVDD Power Sequencing from Buck Regulator
        5. 8.3.3.5 Mixed Mode Buck Operation and Control
        6. 8.3.3.6 Buck Undervoltage Protection
        7. 8.3.3.7 Buck Overcurrent Protection
      4. 8.3.4  AVDD Linear Voltage Regulator
      5. 8.3.5  Charge Pump
      6. 8.3.6  Slew Rate Control
      7. 8.3.7  Cross Conduction (Dead Time)
      8. 8.3.8  SPEED Control
        1. 8.3.8.1 Analog-Mode Speed Control
        2. 8.3.8.2 PWM-Mode Speed Control
        3. 8.3.8.3 I2C based Speed Control
        4. 8.3.8.4 Frequency-Mode Speed Control
      9. 8.3.9  Starting the Motor Under Different Initial Conditions
        1. 8.3.9.1 Case 1 – Motor is Stationary
        2. 8.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 8.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 8.3.10 Motor Start Sequence (MSS)
        1. 8.3.10.1 Initial Speed Detect (ISD)
        2. 8.3.10.2 Motor Resynchronization
        3. 8.3.10.3 Reverse Drive
        4. 8.3.10.4 Motor Start-up
          1. 8.3.10.4.1 Align
          2. 8.3.10.4.2 Double Align
          3. 8.3.10.4.3 Initial Position Detection (IPD)
            1. 8.3.10.4.3.1 IPD Operation
            2. 8.3.10.4.3.2 IPD Release Mode
            3. 8.3.10.4.3.3 IPD Advance Angle
          4. 8.3.10.4.4 Slow First Cycle Startup
          5. 8.3.10.4.5 Open loop
          6. 8.3.10.4.6 Transition from Open to Closed Loop
      11. 8.3.11 Closed Loop Operation
        1. 8.3.11.1 120o Commutation
          1. 8.3.11.1.1 High-Side Modulation
          2. 8.3.11.1.2 Low-Side Modulation
          3. 8.3.11.1.3 Mixed Modulation
        2. 8.3.11.2 Variable Commutation (Available only in MCT8316AV)
        3. 8.3.11.3 Lead Angle Control
        4. 8.3.11.4 Closed loop accelerate
      12. 8.3.12 Speed Loop (Available only in MCT8316AV)
      13. 8.3.13 Input Power Regulation (Available only in MCT8316AV)
      14. 8.3.14 Anti-Voltage Surge (AVS)
      15. 8.3.15 Output PWM Switching Frequency
      16. 8.3.16 Fast Start-up (< 50 ms)
        1. 8.3.16.1 BEMF Threshold
        2. 8.3.16.2 Dynamic Degauss
      17. 8.3.17 Fast Deceleration
      18. 8.3.18 Active Demagnetization
        1. 8.3.18.1 Active Demagnetization in action
      19. 8.3.19 Motor Stop Options
        1. 8.3.19.1 Coast (Hi-Z) Mode
        2. 8.3.19.2 Recirculation Mode
        3. 8.3.19.3 Low-Side Braking
        4. 8.3.19.4 High-Side Braking
        5. 8.3.19.5 Active Spin-Down
      20. 8.3.20 FG Configuration
        1. 8.3.20.1 FG Output Frequency
        2. 8.3.20.2 FG Open-Loop and Lock Behavior
      21. 8.3.21 Protections
        1. 8.3.21.1  VM Supply Undervoltage Lockout
        2. 8.3.21.2  AVDD Undervoltage Lockout (AVDD_UV)
        3. 8.3.21.3  BUCK Undervoltage Lockout (BUCK_UV)
        4. 8.3.21.4  VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 8.3.21.5  Overvoltage Protection (OVP)
        6. 8.3.21.6  Overcurrent Protection (OCP)
          1. 8.3.21.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 8.3.21.6.2 OCP Automatic Retry (OCP_MODE = 01b)
          3. 8.3.21.6.3 OCP Report Only (OCP_MODE = 10b)
          4. 8.3.21.6.4 OCP Disabled (OCP_MODE = 11b)
        7. 8.3.21.7  Buck Overcurrent Protection
        8. 8.3.21.8  Cycle-by-Cycle (CBC) Current Limit (CBC_ILIMIT)
          1. 8.3.21.8.1 CBC_ILIMIT Automatic Recovery next PWM Cycle (CBC_ILIMIT_MODE = 000xb)
          2. 8.3.21.8.2 CBC_ILIMIT Automatic Recovery Threshold Based (CBC_ILIMIT_MODE = 001xb)
          3. 8.3.21.8.3 CBC_ILIMIT Automatic Recovery after 'n' PWM Cycles (CBC_ILIMIT_MODE = 010xb)
          4. 8.3.21.8.4 CBC_ILIMIT Report Only (CBC_ILIMIT_MODE = 0110b)
          5. 8.3.21.8.5 CBC_ILIMIT Disabled (CBC_ILIMIT_MODE = 0111b or 1xxxb)
        9. 8.3.21.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 8.3.21.9.1 LOCK_ILIMIT Latched Shutdown (LOCK_ILIMIT_MODE = 00xxb)
          2. 8.3.21.9.2 LOCK_ILIMIT Automatic Recovery (LOCK_ILIMIT_MODE = 01xxb)
          3. 8.3.21.9.3 LOCK_ILIMIT Report Only (LOCK_ILIMIT_MODE = 1000b)
          4. 8.3.21.9.4 LOCK_ILIMIT Disabled (LOCK_ILIMIT_MODE = 1xx1b)
        10. 8.3.21.10 Thermal Warning (OTW)
        11. 8.3.21.11 Thermal Shutdown (TSD)
        12. 8.3.21.12 Motor Lock (MTR_LCK)
          1. 8.3.21.12.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 8.3.21.12.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 8.3.21.12.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 8.3.21.12.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        13. 8.3.21.13 Motor Lock Detection
          1. 8.3.21.13.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 8.3.21.13.2 Lock 2: Loss of Sync (LOSS_OF_SYNC)
          3. 8.3.21.13.3 Lock3: No-Motor Fault (NO_MTR)
        14. 8.3.21.14 IPD Faults
    4. 8.4 Device Functional Modes
      1. 8.4.1 Functional Modes
        1. 8.4.1.1 Sleep Mode
        2. 8.4.1.2 Standby Mode
        3. 8.4.1.3 Fault Reset (CLR_FLT)
    5. 8.5 External Interface
      1. 8.5.1 DRVOFF Functionality
      2. 8.5.2 DAC outputs
      3. 8.5.3 SOX Output
      4. 8.5.4 Oscillator Source
        1. 8.5.4.1 External Clock Source (Available for MCT8316AV)
      5. 8.5.5 External Watchdog (Available only in MCT836AV)
    6. 8.6 EEPROM access and I2C interface
      1. 8.6.1 EEPROM Access
        1. 8.6.1.1 EEPROM Write
        2. 8.6.1.2 EEPROM Read
      2. 8.6.2 I2C Serial Interface (Available only in MCT8316AV)
        1. 8.6.2.1 I2C Data Word
        2. 8.6.2.2 I2C Write Operation
        3. 8.6.2.3 I2C Read Operation
        4. 8.6.2.4 Examples of MCT8316A I2C Communication Protocol Packets
        5. 8.6.2.5 Internal Buffers
        6. 8.6.2.6 CRC Byte Calculation
    7. 8.7 EEPROM (Non-Volatile) Register Map
      1. 8.7.1 Algorithm_Configuration Registers
      2. 8.7.2 Fault_Configuration Registers
      3. 8.7.3 Hardware_Configuration Registers
      4. 8.7.4 Gate_Driver_Configuration Registers
    8. 8.8 RAM (Volatile) Register Map
      1. 8.8.1 Fault_Status Registers
      2. 8.8.2 System_Status Registers
      3. 8.8.3 Algo_Control Registers
      4. 8.8.4 Device_Control Registers
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application curves
        1. 9.2.1.1 Motor startup
        2. 9.2.1.2 120o and variable commutation
        3. 9.2.1.3 Faster startup time
        4. 9.2.1.4 Setting the BEMF threshold
        5. 9.2.1.5 Maximum speed
        6. 9.2.1.6 Faster deceleration
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
      1. 11.3.1 Power Dissipation
  12. 12Device and Documentation Support
    1. 12.1 Support Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Gate_Driver_Configuration Registers

#GATE_DRIVER_CONFIGURATION_GATE_DRIVER_CONFIGURATION_TABLE_1 lists the memory-mapped registers for the Gate_Driver_Configuration registers. All register offset addresses not listed in #GATE_DRIVER_CONFIGURATION_GATE_DRIVER_CONFIGURATION_TABLE_1 should be considered as reserved locations and the register contents should not be modified.

Table 8-50 GATE_DRIVER_CONFIGURATION Registers
AddressAcronymRegister NameSection
AChGD_CONFIG1Gate driver configuration 1#GATE_DRIVER_CONFIGURATION_GATE_DRIVER_CONFIGURATION_GATE_DRIVER_CONFIGURATION_GD_CONFIG1
AEhGD_CONFIG2Gate driver configuration 2#GATE_DRIVER_CONFIGURATION_GATE_DRIVER_CONFIGURATION_GATE_DRIVER_CONFIGURATION_GD_CONFIG2

Complex bit access types are encoded to fit into small table cells. #GATE_DRIVER_CONFIGURATION_GATE_DRIVER_CONFIGURATION_LEGEND shows the codes that are used for access types in this section.

Table 8-51 Gate_Driver_Configuration Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.7.4.1 GD_CONFIG1 Register (Address = ACh) [Reset = 00228000h]

GD_CONFIG1 is shown in #GATE_DRIVER_CONFIGURATION_GATE_DRIVER_CONFIGURATION_GATE_DRIVER_CONFIGURATION_GD_CONFIG1_FIGURE and described in #GATE_DRIVER_CONFIGURATION_GATE_DRIVER_CONFIGURATION_GATE_DRIVER_CONFIGURATION_GD_CONFIG1_TABLE.

Return to the Summary Table.

Register to configure gated driver settings1

Figure 8-72 GD_CONFIG1 Register
3130292827262524
PARITYRESERVEDRESERVEDSLEW_RATERESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDOVP_SELOVP_ENRESERVEDOTW_REP
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1hR/W-0h
15141312111098
RESERVEDRESERVEDOCP_DEGOCP_RETRYOCP_LVLOCP_MODE
R/W-1hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDADCOMP_TH_LSADCOMP_TH_HSEN_ASREN_AARCSA_GAIN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 8-52 GD_CONFIG1 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-29RESERVEDR/W0h Reserved
28RESERVEDR/W0h Reserved
27-26SLEW_RATER/W0h Slew rate

0h = 25 V/µs

1h = 50 V/µs

2h = 125 V/µs

3h = 200 V/µs

25-24RESERVEDR/W0h Reserved
23RESERVEDR/W0h Reserved
22RESERVEDR/W0h Reserved
21RESERVEDR/W1h Reserved
20RESERVEDR/W0h Reserved
19OVP_SELR/W0h Overvoltage protection level

0h = VM overvoltage level is 32-V

1h = VM overvoltage level is 20-V

18OVP_ENR/W0h Overvoltage protection enable

0h = Disable

1h = Enable

17RESERVEDR/W1h Reserved
16OTW_REPR/W0h Overtemperature warning reporting on nFAULT

0h = Over temperature reporting on nFAULT is disabled

1h = Over temperature reporting on nFAULT is enabled

15RESERVEDR/W1h Reserved
14RESERVEDR/W0h Reserved
13-12OCP_DEGR/W0h OCP deglitch time

0h = 0.2 µs

1h = 0.6 µs

2h = 1.1 µs

3h = 1.6 µs

11OCP_RETRYR/W0h OCP retry time

0h = 5 ms

1h = 500 ms

10OCP_LVLR/W0h OCP level

0h = 16 A (Typical)

1h = 24 A (Typical)

9-8OCP_MODER/W0h OCP fault mode

0h = Overcurrent causes a latched fault

1h = Overcurrent causes an automatic retrying fault

2h = Overcurrent is report only but no action is taken

3h = Overcurrent is not reported and no action is taken

7RESERVEDR/W0h Reserved
6RESERVEDR/W0h Reserved
5ADCOMP_TH_LSR/W0h Active demag comparator threshold for low-side

0h = 100 mA

1h = 150 mA

4ADCOMP_TH_HSR/W0h Active demag comparator threshold for high-side

0h = 100 mA

1h = 150 mA

3EN_ASRR/W0h Active synchronous rectification enable

0h = Disable

1h = Enable

2EN_AARR/W0h Active asynchronous rectification enable

0h = Disable

1h = Enable

1-0CSA_GAINR/W0h Current Sense Amplifier (CSA) Gain

0h = 0.15 V/A

1h = 0.3 V/A

2h = 0.6 V/A

3h = 1.2 V/A

8.7.4.2 GD_CONFIG2 Register (Address = AEh) [Reset = 01200000h]

GD_CONFIG2 is shown in #GATE_DRIVER_CONFIGURATION_GATE_DRIVER_CONFIGURATION_GATE_DRIVER_CONFIGURATION_GD_CONFIG2_FIGURE and described in #GATE_DRIVER_CONFIGURATION_GATE_DRIVER_CONFIGURATION_GATE_DRIVER_CONFIGURATION_GD_CONFIG2_TABLE.

Return to the Summary Table.

Register to configure gated driver settings2

Figure 8-73 GD_CONFIG2 Register
3130292827262524
PARITYDELAY_COMP_ENTARGET_DELAYBUCK_SRBUCK_PS_DIS
R/W-0hR/W-0hR/W-0hR/W-0hR/W-1h
2322212019181716
BUCK_CLBUCK_SELBUCK_DISRESERVED
R/W-0hR/W-1hR/W-0hR/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVED
R/W-0h
Table 8-53 GD_CONFIG2 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30DELAY_COMP_ENR/W0h Driver delay compensation enable

0h = Disable

1h = Enable

29-26TARGET_DELAYR/W0h Target delay

0h = Automatic based on slew rate

1h = 0.4 µs

2h = 0.6 µs

3h = 0.8 µs

4h = 1 µs

5h = 1.2 µs

6h = 1.4 µs

7h = 1.6 µs

8h = 1.8 µs

9h = 2 µs

Ah = 2.2 µs

Bh = 2.4 µs

Ch = 2.6 µs

Dh = 2.8 µs

Eh = 3 µs

Fh = 3.2 µs

25BUCK_SRR/W0h Buck slew rate

0h = Buck's FET slew rate is 1000V/µs

1h = Buck's FET slew rate is 200V/µs

24BUCK_PS_DISR/W1h Buck power sequencing disable

0h = Buck power sequencing is enabled

1h = Buck power sequencing is disabled

23BUCK_CLR/W0h Buck current limit

0h = 600 mA

1h = 150 mA

22-21BUCK_SELR/W1h Buck voltage selection

0h = Buck voltage is 3.3 V

1h = Buck voltage is 5.0 V

2h = Buck voltage is 4.0 V

3h = Buck voltage is 5.7 V

20BUCK_DISR/W0h Buck disable

0h = Buck regulator is enabled

1h = Buck regulator is disabled

19-0RESERVEDR/W0h Reserved