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1Features
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2Applications
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3Description
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4Functional Block Diagram
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5Revision History
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6Terminal Configuration and Functions
- 6.1
Pin Diagrams
- 6.2
Signal Descriptions
- 6.2.1
Terminal Functions
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7Specifications
- 7.1
Absolute Maximum Ratings
- 7.2
ESD Ratings
- 7.3
Recommended Operating Conditions
- 7.4
Active Mode Supply Current Into VCC Excluding External Current
- 7.5
Low-Power Mode Supply Currents (Into VCC) Excluding External Current
- 7.6
Thermal Characteristics
- 7.7
Schmitt-Trigger Inputs – General-Purpose I/O
- 7.8
Inputs – Ports P1 and P2
- 7.9
Leakage Current – General-Purpose I/O
- 7.10
Outputs – General-Purpose I/O (Full Drive Strength)
- 7.11
Outputs – General-Purpose I/O (Reduced Drive Strength)
- 7.12
Output Frequency – General-Purpose I/O
- 7.13
Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
- 7.14
Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
- 7.15
Crystal Oscillator, XT1, Low-Frequency Mode
- 7.16
Crystal Oscillator, XT1, High-Frequency Mode
- 7.17
Crystal Oscillator, XT2
- 7.18
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
- 7.19
Internal Reference, Low-Frequency Oscillator (REFO)
- 7.20
DCO Frequency
- 7.21
PMM, Brown-Out Reset (BOR)
- 7.22
PMM, Core Voltage
- 7.23
PMM, SVS High Side
- 7.24
PMM, SVM High Side
- 7.25
PMM, SVS Low Side
- 7.26
PMM, SVM Low Side
- 7.27
Wake-up Times From Low-Power Modes and Reset
- 7.28
Timer_A
- 7.29
Timer_B
- 7.30
USCI (UART Mode), Recommended Operating Conditions
- 7.31
USCI (UART Mode)
- 7.32
USCI (SPI Master Mode), Recommended Operating Conditions
- 7.33
USCI (SPI Master Mode)
- 7.34
USCI (SPI Slave Mode)
- 7.35
USCI (I2C Mode)
- 7.36
12-Bit ADC, Power Supply and Input Range Conditions
- 7.37
12-Bit ADC, Timing Parameters
- 7.38
12-Bit ADC, Linearity Parameters
- 7.39
12-Bit ADC, Temperature Sensor and Built-In VMID
- 7.40
REF, External Reference
- 7.41
REF, Built-In Reference
- 7.42
Flash Memory
- 7.43
JTAG and Spy-Bi-Wire Interface
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8Detailed Description
- 8.1
CPU
- 8.2
Operating Modes
- 8.3
Interrupt Vector Addresses
- 8.4
Memory Organization
- 8.5
Bootstrap Loader (BSL)
- 8.6
JTAG Operation
- 8.6.1
JTAG Standard Interface
- 8.6.2
Spy-Bi-Wire Interface
- 8.7
Flash Memory
- 8.8
RAM
- 8.9
Peripherals
- 8.9.1
Digital I/O
- 8.9.2
Oscillator and System Clock
- 8.9.3
Power-Management Module (PMM)
- 8.9.4
Hardware Multiplier (MPY)
- 8.9.5
Real-Time Clock (RTC_A)
- 8.9.6
Watchdog Timer (WDT_A)
- 8.9.7
System Module (SYS)
- 8.9.8
DMA Controller
- 8.9.9
Universal Serial Communication Interface (USCI)
- 8.9.10
TA0
- 8.9.11
TA1
- 8.9.12
TB0
- 8.9.13
ADC12_A
- 8.9.14
CRC16
- 8.9.15
REF Voltage Reference
- 8.9.16
Embedded Emulation Module (EEM) (L Version)
- 8.9.17
Peripheral File Map
- 8.10
Input/Output Schematics
- 8.10.1
Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
- 8.10.2
Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger
- 8.10.3
Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger
- 8.10.4
Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
- 8.10.5
Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
- 8.10.6
Port P5, P5.2, Input/Output With Schmitt Trigger
- 8.10.7
Port P5, P5.3, Input/Output With Schmitt Trigger
- 8.10.8
Port P5, P5.4 to P5.7, Input/Output With Schmitt Trigger
- 8.10.9
Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger
- 8.10.10
Port P7, P7.0, Input/Output With Schmitt Trigger
- 8.10.11
Port P7, P7.1, Input/Output With Schmitt Trigger
- 8.10.12
Port P7, P7.2 and P7.3, Input/Output With Schmitt Trigger
- 8.10.13
Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger
- 8.10.14
Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger
- 8.10.15
Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger
- 8.10.16
Port P10, P10.0 to P10.7, Input/Output With Schmitt Trigger
- 8.10.17
Port P11, P11.0 to P11.2, Input/Output With Schmitt Trigger
- 8.10.18
Port J, J.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
- 8.10.19
Port J, J.1 to J.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
- 8.11
Device Descriptors (TLV)
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9Device and Documentation Support
- 9.1
Device Support
- 9.1.1
Getting Started and Next Steps
- 9.1.2
Development Tools Support
- 9.1.2.1
Hardware Features
- 9.1.2.2
Recommended Hardware Options
- 9.1.2.2.1
Experimenter Boards
- 9.1.2.2.2
Debugging and Programming Tools
- 9.1.2.2.3
Production Programmers
- 9.1.2.3
Recommended Software Options
- 9.1.2.3.1
Integrated Development Environments
- 9.1.2.3.2
MSP430Ware
- 9.1.2.3.3
TI-RTOS
- 9.1.2.3.4
Command-Line Programmer
- 9.1.3
Device Nomenclature
- 9.2
Documentation Support
- 9.3
Support Resources
- 9.4
Trademarks
- 9.5
Electrostatic Discharge Caution
- 9.6
Export Control Notice
- 9.7
Glossary
Package Options
Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information