SLAS703B April   2010  – August 2015 MSP430BT5190

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Characteristics
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Thermal Characteristics
    7. 5.7  Schmitt-Trigger Inputs - General-Purpose I/O
    8. 5.8  Inputs - Ports P1 and P2
    9. 5.9  Leakage Current - General-Purpose I/O
    10. 5.10 Outputs - General-Purpose I/O (Full Drive Strength)
    11. 5.11 Outputs - General-Purpose I/O (Reduced Drive Strength)
    12. 5.12 Output Frequency - General-Purpose I/O
    13. 5.13 Typical Characteristics - Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 5.14 Typical Characteristics - Outputs, Full Drive Strength (PxDS.y = 1)
    15. 5.15 Crystal Oscillator, XT1, Low-Frequency Mode
    16. 5.16 Crystal Oscillator, XT1, High-Frequency Mode
    17. 5.17 Crystal Oscillator, XT2
    18. 5.18 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    19. 5.19 Internal Reference, Low-Frequency Oscillator (REFO)
    20. 5.20 DCO Frequency
    21. 5.21 PMM, Brown-Out Reset (BOR)
    22. 5.22 PMM, Core Voltage
    23. 5.23 PMM, SVS High Side
    24. 5.24 PMM, SVM High Side
    25. 5.25 PMM, SVS Low Side
    26. 5.26 PMM, SVM Low Side
    27. 5.27 Wake-up Times From Low-Power Modes and Reset
    28. 5.28 Timer_A
    29. 5.29 Timer_B
    30. 5.30 USCI (UART Mode), Recommended Operating Conditions
    31. 5.31 USCI (UART Mode)
    32. 5.32 USCI (SPI Master Mode), Recommended Operating Conditions
    33. 5.33 USCI (SPI Master Mode)
    34. 5.34 USCI (SPI Slave Mode)
    35. 5.35 USCI (I2C Mode)
    36. 5.36 12-Bit ADC, Power Supply and Input Range Conditions
    37. 5.37 12-Bit ADC, Timing Parameters
    38. 5.38 12-Bit ADC, Linearity Parameters
    39. 5.39 12-Bit ADC, Temperature Sensor and Built-In VMID
    40. 5.40 REF, External Reference
    41. 5.41 REF, Built-In Reference
    42. 5.42 Flash Memory
    43. 5.43 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Operating Modes
    3. 6.3  Interrupt Vector Addresses
    4. 6.4  Memory Organization
    5. 6.5  Bootstrap Loader (BSL)
    6. 6.6  JTAG Operation
      1. 6.6.1 JTAG Standard Interface
      2. 6.6.2 Spy-Bi-Wire Interface
    7. 6.7  Flash Memory
    8. 6.8  RAM
    9. 6.9  Peripherals
      1. 6.9.1  Digital I/O
      2. 6.9.2  Oscillator and System Clock
      3. 6.9.3  Power-Management Module (PMM)
      4. 6.9.4  Hardware Multiplier (MPY)
      5. 6.9.5  Real-Time Clock (RTC_A)
      6. 6.9.6  Watchdog Timer (WDT_A)
      7. 6.9.7  System Module (SYS)
      8. 6.9.8  DMA Controller
      9. 6.9.9  Universal Serial Communication Interface (USCI)
      10. 6.9.10 TA0
      11. 6.9.11 TA1
      12. 6.9.12 TB0
      13. 6.9.13 ADC12_A
      14. 6.9.14 CRC16
      15. 6.9.15 REF Voltage Reference
      16. 6.9.16 Embedded Emulation Module (EEM) (L Version)
      17. 6.9.17 Peripheral File Map
    10. 6.10 Input/Output Schematics
      1. 6.10.1  Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
      2. 6.10.2  Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger
      3. 6.10.3  Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger
      4. 6.10.4  Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
      5. 6.10.5  Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
      6. 6.10.6  Port P5, P5.2, Input/Output With Schmitt Trigger
      7. 6.10.7  Port P5, P5.3, Input/Output With Schmitt Trigger
      8. 6.10.8  Port P5, P5.4 to P5.7, Input/Output With Schmitt Trigger
      9. 6.10.9  Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger
      10. 6.10.10 Port P7, P7.0, Input/Output With Schmitt Trigger
      11. 6.10.11 Port P7, P7.1, Input/Output With Schmitt Trigger
      12. 6.10.12 Port P7, P7.2 and P7.3, Input/Output With Schmitt Trigger
      13. 6.10.13 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger
      14. 6.10.14 Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger
      15. 6.10.15 Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger
      16. 6.10.16 Port P10, P10.0 to P10.7, Input/Output With Schmitt Trigger
      17. 6.10.17 Port P11, P11.0 to P11.2, Input/Output With Schmitt Trigger
      18. 6.10.18 Port J, J.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      19. 6.10.19 Port J, J.1 to J.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    11. 6.11 Device Descriptors (TLV)
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Getting Started and Next Steps
      2. 7.1.2 Development Tools Support
        1. 7.1.2.1 Hardware Features
        2. 7.1.2.2 Recommended Hardware Options
          1. 7.1.2.2.1 Experimenter Boards
          2. 7.1.2.2.2 Debugging and Programming Tools
          3. 7.1.2.2.3 Production Programmers
        3. 7.1.2.3 Recommended Software Options
          1. 7.1.2.3.1 Integrated Development Environments
          2. 7.1.2.3.2 MSP430Ware
          3. 7.1.2.3.3 TI-RTOS
          4. 7.1.2.3.4 Command-Line Programmer
      3. 7.1.3 Device and Development Tool Nomenclature
    2. 7.2 Documentation Support
    3. 7.3 Community Resources
    4. 7.4 Trademarks
    5. 7.5 Electrostatic Discharge Caution
    6. 7.6 Export Control Notice
    7. 7.7 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Detailed Description

6.1 CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions.

The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data.

MSP430BT5190 slas703-040.gif

6.2 Operating Modes

The MSP430 has one active mode and six software selectable low-power modes of operation. An interrupt event can wake up the device from any of the low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.

The following operating modes can be configured by software:

  • Active mode (AM)
    • All clocks are active
  • Low-power mode 0 (LPM0)
    • CPU is disabled
    • ACLK and SMCLK remain active
    • MCLK is disabled
    • FLL loop control remains active
  • Low-power mode 1 (LPM1)
    • CPU is disabled
    • FLL loop control is disabled
    • ACLK and SMCLK remain active
    • MCLK is disabled
  • Low-power mode 2 (LPM2)
    • CPU is disabled
    • MCLK, FLL loop control, and DCOCLK are disabled
    • DCO DC generator remains enabled
    • ACLK remains active
  • Low-power mode 3 (LPM3)
    • CPU is disabled
    • MCLK, FLL loop control, and DCOCLK are disabled
    • DCO DC generator is disabled
    • ACLK remains active
  • Low-power mode 4 (LPM4)
    • CPU is disabled
    • ACLK is disabled
    • MCLK, FLL loop control, and DCOCLK are disabled
    • DCO DC generator is disabled
    • Crystal oscillator is stopped
    • Complete data retention
  • Low-power mode 4.5 (LPM4.5)
    • Internal regulator disabled
    • No data retention
    • Wake-up signal from RST, digital I/O

6.3 Interrupt Vector Addresses

The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 6-1 Interrupt Sources, Flags, and Vectors

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
System Reset
Power-Up
External Reset
Watchdog Time-out, Password Violation
Flash Memory Password Violation
PMM Password Violation
WDTIFG, KEYV (SYSRSTIV)(1)(3) Reset 0FFFEh 63, highest
System NMI
PMM
Vacant Memory Access
JTAG Mailbox
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG, VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, JMBOUTIFG (SYSSNIV)(1) (Non)maskable 0FFFCh 62
User NMI
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG, OFIFG, ACCVIFG (SYSUNIV)(1)(3) (Non)maskable 0FFFAh 61
TB0 TBCCR0 CCIFG0 (2) Maskable 0FFF8h 60
TB0 TBCCR1 CCIFG1 ... TBCCR6 CCIFG6,
TBIFG (TBIV)(1)(2)
Maskable 0FFF6h 59
Watchdog Timer_A Interval Timer Mode WDTIFG Maskable 0FFF4h 58
USCI_A0 Receive or Transmit UCA0RXIFG, UCA0TXIFG (UCA0IV)(1)(2) Maskable 0FFF2h 57
USCI_B0 Receive or Transmit UCB0RXIFG, UCB0TXIFG (UCAB0IV)(1)(2) Maskable 0FFF0h 56
ADC12_A ADC12IFG0 ... ADC12IFG15 (ADC12IV)(1)(2) Maskable 0FFEEh 55
TA0 TA0CCR0 CCIFG0(2) Maskable 0FFECh 54
TA0 TA0CCR1 CCIFG1 ... TA0CCR4 CCIFG4,
TA0IFG (TA0IV)(1)(2)
Maskable 0FFEAh 53
USCI_A2 Receive or Transmit UCA2RXIFG, UCA2TXIFG (UCA2IV)(1)(2) Maskable 0FFE8h 52
USCI_B2 Receive or Transmit UCB2RXIFG, UCB2TXIFG (UCB2IV)(1)(2) Maskable 0FFE6h 51
DMA DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)(1)(2) Maskable 0FFE4h 50
TA1 TA1CCR0 CCIFG0(2) Maskable 0FFE2h 49
TA1 TA1CCR1 CCIFG1 ... TA1CCR2 CCIFG2,
TA1IFG (TA1IV)(1)(2)
Maskable 0FFE0h 48
I/O Port P1 P1IFG.0 to P1IFG.7 (P1IV)(1)(2) Maskable 0FFDEh 47
USCI_A1 Receive or Transmit UCA1RXIFG, UCA1TXIFG (UCA1IV)(1)(2) Maskable 0FFDCh 46
USCI_B1 Receive or Transmit UCB1RXIFG, UCB1TXIFG (UCB1IV)(1)(2) Maskable 0FFDAh 45
USCI_A3 Receive or Transmit UCA3RXIFG, UCA3TXIFG (UCA3IV)(1)(2) Maskable 0FFD8h 44
USCI_B3 Receive or Transmit UCB3RXIFG, UCB3TXIFG (UCB3IV)(1)(2) Maskable 0FFD6h 43
I/O Port P2 P2IFG.0 to P2IFG.7 (P2IV)(1)(2) Maskable 0FFD4h 42
RTC_A RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG, RT1PSIFG (RTCIV)(1)(2) Maskable 0FFD2h 41
Reserved Reserved(4) 0FFD0h 40
0FF80h 0, lowest
(1) Multiple source flags
(2) Interrupt flags are located in the module.
(3) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(4) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain compatibility with other devices, TI recommends reserving these locations.

6.4 Memory Organization

Table 6-2 lists the memory locations and sizes for the device.

Table 6-2 Memory Organization

MSP430BT5190
Memory (flash)
Main: interrupt vector
Main: code memory
Total Size
Flash
Flash
256KB
00FFFFh–00FF80h
045BFFh–005C00h
Main: code memory Bank D 64KB
03FFFFh–030000h
Bank C 64KB
02FFFFh–020000h
Bank B 64KB
01FFFFh–010000h
Bank A 64KB
045BFFh–040000h
00FFFFh–005C00h
RAM Size 16KB
Sector 3 4KB
005BFFh–004C00h
Sector 2 4KB
004BFFh–003C00h
Sector 1 4KB
003BFFh–002C00h
Sector 0 4KB
002BFFh–001C00h
Information memory (flash) Info A 128 B
0019FFh–001980h
Info B 128 B
00197Fh–001900h
Info C 128 B
0018FFh–001880h
Info D 128 B
00187Fh–001800h
Bootstrap loader (BSL) memory (Flash) BSL 3 512 B
0017FFh–001600h
BSL 2 512 B
0015FFh–001400h
BSL 1 512 B
0013FFh–001200h
BSL 0 512 B
0011FFh–001000h
Peripherals Size 4KB
000FFFh–000000h

6.5 Bootstrap Loader (BSL)

The BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the device memory through the BSL is protected by an user-defined password. Usage of the BSL requires four pins as shown in Table 6-3. BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For further details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide (SLAU278). For a complete description of the features of the BSL and its implementation, see the MSP430 Programming Via the Bootstrap Loader User's Guide (SLAU319).

Table 6-3 BSL Pin Requirements and Functions

DEVICE SIGNAL BSL FUNCTION
RST/NMI/SBWTDIO Entry sequence signal
TEST/SBWTCK Entry sequence signal
P1.1 Data transmit
P1.2 Data receive
VCC Power supply
VSS Ground supply

6.6 JTAG Operation

6.6.1 JTAG Standard Interface

The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430 development tools and device programmers. The JTAG pin requirements are shown in Table 6-4. For further details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide (SLAU278). For a complete description of the features of the JTAG interface and its implementation, see MSP430 Programming Via the JTAG Interface (SLAU320).

Table 6-4 JTAG Pin Requirements and Functions

DEVICE SIGNAL DIRECTION FUNCTION
PJ.3/TCK IN JTAG clock input
PJ.2/TMS IN JTAG state control
PJ.1/TDI/TCLK IN JTAG data input; TCLK input
PJ.0/TDO OUT JTAG data output
TEST/SBWTCK IN Enable JTAG pins
RST/NMI/SBWTDIO IN External reset
VCC Power supply
VSS Ground supply

6.6.2 Spy-Bi-Wire Interface

In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface. Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire interface pin requirements are shown in Table 6-5. For further details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide (SLAU278). For a complete description of the features of the JTAG interface and its implementation, see MSP430 Programming Via the JTAG Interface (SLAU320).

Table 6-5 Spy-Bi-Wire Pin Requirements and Functions

DEVICE SIGNAL DIRECTION FUNCTION
TEST/SBWTCK IN Spy-Bi-Wire clock input
RST/NMI/SBWTDIO IN, OUT Spy-Bi-Wire data input/output
VCC Power supply
VSS Ground supply

6.7 Flash Memory

The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the flash memory include:

  • Flash memory has n segments of main memory and four segments of information memory (A to D) of 128 bytes each. Each segment in main memory is 512 bytes in size.
  • Segments 0 to n may be erased in one step, or each segment may be individually erased.
  • Segments A to D can be erased individually. Segments A to D are also called information memory.
  • Segment A can be locked separately.

6.8 RAM

The RAM is made up of n sectors. Each sector can be completely powered down to save leakage; however, all data is lost. Features of the RAM include:

  • RAM has n sectors. The size of a sector can be found in Memory Organization.
  • Each sector 0 to n can be complete disabled; however, data retention is lost.
  • Each sector 0 to n automatically enters low-power retention mode when possible.

6.9 Peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).

6.9.1 Digital I/O

There are up to ten 8-bit I/O ports implemented: For 100-pin options, P1 through P10 are complete. P11 contains three individual I/O ports. For 80-pin options, P1 through P7 are complete. P8 contains seven individual I/O ports. P9 through P11 do not exist. Port PJ contains four individual I/O ports, common to all devices.

  • All individual I/O bits are independently programmable.
  • Any combination of input, output, and interrupt conditions is possible.
  • Pullup or pulldown on all ports is programmable.
  • Drive strength on all ports is programmable.
  • Edge-selectable interrupt and LPM4.5 wakeup input capability is available for all bits of ports P1 and P2.
  • Read and write access to port-control registers is supported by all instructions.
  • Ports can be accessed byte-wise (P1 through P11) or word-wise in pairs (PA through PF).

6.9.2 Oscillator and System Clock

The clock system is supported by the Unified Clock System (UCS) module that includes support for a 32-kHz watch crystal oscillator (XT1 LF mode), an internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), an integrated internal digitally controlled oscillator (DCO), and a high-frequency crystal oscillator (XT1 HF mode or XT2). The UCS module is designed to meet the requirements of both low system cost and low power consumption. The UCS module features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the selected FLL reference frequency. The internal DCO provides a fast turnon clock source and stabilizes in less than 5 µs. The UCS module provides the following clock signals:

  • Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal, a high-frequency crystal, the internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal digitally controlled oscillator DCO.
  • Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made available to ACLK.
  • Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by same sources made available to ACLK.
  • ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.

6.9.3 Power-Management Module (PMM)

The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor (SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is implemented to provide the proper internal reset signal to the device during power-on and power-off. The SVS and SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.

6.9.4 Hardware Multiplier (MPY)

The multiplication operation is supported by a dedicated peripheral module. The module performs operations with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication as well as signed and unsigned multiply-and-accumulate operations.

6.9.5 Real-Time Clock (RTC_A)

The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated real-time clock (RTC) (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. Calendar mode integrates an internal calendar which compensates for months with less than 31 days and includes leap year correction. The RTC_A also supports flexible alarm functions and offset-calibration hardware.

6.9.6 Watchdog Timer (WDT_A)

The primary function of the WDT_A module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.

6.9.7 System Module (SYS)

The SYS module handles many of the system functions within the device. These include power-on reset and power-up clear handling, NMI source selection and management, reset interrupt vector generators, bootstrap loader entry mechanisms, and configuration management (device descriptors). It also includes a data exchange mechanism through JTAG called a JTAG mailbox that can be used in the application.

Table 6-6 System Module Interrupt Vector Registers

INTERRUPT VECTOR REGISTER ADDRESS INTERRUPT EVENT VALUE PRIORITY
SYSRSTIV, System Reset 019Eh No interrupt pending 00h
Brownout (BOR) 02h Highest
RST/NMI (POR) 04h
PMMSWBOR (BOR) 06h
Wakeup from LPMx.5 08h
Security violation (BOR) 0Ah
SVSL (POR) 0Ch
SVSH (POR) 0Eh
SVML_OVP (POR) 10h
SVMH_OVP (POR) 12h
PMMSWPOR (POR) 14h
WDT time-out (PUC) 16h
WDT password violation (PUC) 18h
KEYV flash password violation (PUC) 1Ah
Reserved 1Ch
Peripheral area fetch (PUC) 1Eh
PMM password violation (PUC) 20h
Reserved 22h to 3Eh Lowest
SYSSNIV, System NMI 019Ch No interrupt pending 00h
SVMLIFG 02h Highest
SVMHIFG 04h
SVSMLDLYIFG 06h
SVSMHDLYIFG 08h
VMAIFG 0Ah
JMBINIFG 0Ch
JMBOUTIFG 0Eh
SVMLVLRIFG 10h
SVMHVLRIFG 12h
Reserved 14h to 1Eh Lowest
SYSUNIV, User NMI 019Ah No interrupt pending 00h
NMIIFG 02h Highest
OFIFG 04h
ACCVIFG 06h
Reserved 08h
Reserved 0Ah to 1Eh Lowest

6.9.8 DMA Controller

The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC12_A conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or from a peripheral.

Table 6-7 DMA Trigger Assignments(1)

TRIGGER CHANNEL
0 1 2
0 DMAREQ DMAREQ DMAREQ
1 TA0CCR0 CCIFG TA0CCR0 CCIFG TA0CCR0 CCIFG
2 TA0CCR2 CCIFG TA0CCR2 CCIFG TA0CCR2 CCIFG
3 TA1CCR0 CCIFG TA1CCR0 CCIFG TA1CCR0 CCIFG
4 TA1CCR2 CCIFG TA1CCR2 CCIFG TA1CCR2 CCIFG
5 TB0CCR0 CCIFG TB0CCR0 CCIFG TB0CCR0 CCIFG
6 TB0CCR2 CCIFG TB0CCR2 CCIFG TB0CCR2 CCIFG
7 Reserved Reserved Reserved
8 Reserved Reserved Reserved
9 Reserved Reserved Reserved
10 Reserved Reserved Reserved
11 Reserved Reserved Reserved
12 Reserved Reserved Reserved
13 Reserved Reserved Reserved
14 Reserved Reserved Reserved
15 Reserved Reserved Reserved
16 UCA0RXIFG UCA0RXIFG UCA0RXIFG
17 UCA0TXIFG UCA0TXIFG UCA0TXIFG
18 UCB0RXIFG UCB0RXIFG UCB0RXIFG
19 UCB0TXIFG UCB0TXIFG UCB0TXIFG
20 UCA1RXIFG UCA1RXIFG UCA1RXIFG
21 UCA1TXIFG UCA1TXIFG UCA1TXIFG
22 UCB1RXIFG UCB1RXIFG UCB1RXIFG
23 UCB1TXIFG UCB1TXIFG UCB1TXIFG
24 ADC12IFGx ADC12IFGx ADC12IFGx
25 Reserved Reserved Reserved
26 Reserved Reserved Reserved
27 Reserved Reserved Reserved
28 Reserved Reserved Reserved
29 MPY ready MPY ready MPY ready
30 DMA2IFG DMA0IFG DMA1IFG
31 DMAE0 DMAE0 DMAE0
(1) Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers do not cause any DMA trigger event when selected.

6.9.9 Universal Serial Communication Interface (USCI)

The USCI modules are used for serial data communication. The USCI module supports synchronous communication protocols such as SPI (3-pin or 4-pin) and I2C, and asynchronous communication protocols such as UART, enhanced UART with automatic baud-rate detection, and IrDA. Each USCI module contains two portions, A and B.

The USCI_An module provides support for SPI (3-pin or 4-pin), UART, enhanced UART, or IrDA.

The USCI_Bn module provides support for SPI (3-pin or 4-pin) or I2C.

The MSP430BT5190 includes four complete USCI modules (n = 0 to 3).

6.9.10 TA0

TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. TA0 can support multiple capture/compare registers, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 6-8 TA0 Signal Connections

INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT SIGNAL MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL OUTPUT PIN NUMBER
PZ, ZQW PZ, ZQW
17, H1-P1.0 TA0CLK TACLK Timer NA NA
ACLK ACLK
SMCLK SMCLK
17, H1-P1.0 TA0CLK TACLK
18, H4-P1.1 TA0.0 CCI0A CCR0 TA0 TA0.0 18, H4-P1.1
57, H9-P8.0 TA0.0 CCI0B 57, H9-P8.0
DVSS GND ADC12 (internal)
ADC12SHSx = \{1\}
DVCC VCC
19, J4-P1.2 TA0.1 CCI1A CCR1 TA1 TA0.1 19, J4-P1.2
58, H11-P8.1 TA0.1 CCI1B 58, H11-P8.1
DVSS GND
DVCC VCC
20, J1-P1.3 TA0.2 CCI2A CCR2 TA2 TA0.2 20, J1-P1.3
59, H12-P8.2 TA0.2 CCI2B 59, H12-P8.2
DVSS GND
DVCC VCC
21, J2-P1.4 TA0.3 CCI3A CCR3 TA3 TA0.3 21, J2-P1.4
60, G9-P8.3 TA0.3 CCI3B 60, G9-P8.3
DVSS GND
DVCC VCC
22, K1-P1.5 TA0.4 CCI4A CCR4 TA4 TA0.4 22, K1-P1.5
61, G11-P8.4 TA0.4 CCI4B 61, G11-P8.4
DVSS GND
DVCC VCC

6.9.11 TA1

TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA1 can support multiple capture/compare registers, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 6-9 TA1 Signal Connections

INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT SIGNAL MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL OUTPUT PIN NUMBER
PZ, ZQW PZ, ZQW
25, M1-P2.0 TA1CLK TACLK Timer NA NA
ACLK ACLK
SMCLK SMCLK
25, M1-P2.0 TA1CLK TACLK
26, L2-P2.1 TA1.0 CCI0A CCR0 TA0 TA1.0 26, L2-P2.1
65, F11-P8.5 TA1.0 CCI0B 65, F11-P8.5
DVSS GND
DVCC VCC
27, M2-P2.2 TA1.1 CCI1A CCR1 TA1 TA1.1 27, M2-P2.2
66, E11-P8.6 TA1.1 CCI1B 66, E11-P8.6
DVSS GND
DVCC VCC
28, L3-P2.3 TA1.2 CCI2A CCR2 TA2 TA1.2 28, L3-P2.3
56, J12-P7.3 TA1.2 CCI2B 56, J12-P7.3
DVSS GND
DVCC VCC

6.9.12 TB0

TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. TB0 can support multiple capture/compare registers, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 6-10 TB0 Signal Connections

INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT SIGNAL MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL OUTPUT PIN NUMBER
PZ, ZQW PZ, ZQW
50, M12-P4.7 TB0CLK TBCLK Timer NA NA
ACLK ACLK
SMCLK SMCLK
50, M12-P4.7 TB0CLK TBCLK
43, J8-P4.0 TB0.0 CCI0A CCR0 TB0 TB0.0 43, J8-P4.0
43, J8-P4.0 TB0.0 CCI0B ADC12 (internal)
ADC12SHSx = \{2\}
DVSS GND
DVCC VCC
44, M9-P4.1 TB0.1 CCI1A CCR1 TB1 TB0.1 44, M9-P4.1
44, M9-P4.1 TB0.1 CCI1B ADC12 (internal)
ADC12SHSx = \{3\}
DVSS GND
DVCC VCC
45, L9-P4.2 TB0.2 CCI2A CCR2 TB2 TB0.2 45, L9-P4.2
45, L9-P4.2 TB0.2 CCI2B
DVSS GND
DVCC VCC
46, L10-P4.3 TB0.3 CCI3A CCR3 TB3 TB0.3 46, L10-P4.3
46, L10-P4.3 TB0.3 CCI3B
DVSS GND
DVCC VCC
47, M10-P4.4 TB0.4 CCI4A CCR4 TB4 TB0.4 47, M10-P4.4
47, M10-P4.4 TB0.4 CCI4B
DVSS GND
DVCC VCC
48, L11-P4.5 TB0.5 CCI5A CCR5 TB5 TB0.5 48, L11-P4.5
48, L11-P4.5 TB0.5 CCI5B
DVSS GND
DVCC VCC
49, M11-P4.6 TB0.6 CCI6A CCR6 TB6 TB0.6 49, M11-P4.6
ACLK (internal) CCI6B
DVSS GND
DVCC VCC

6.9.13 ADC12_A

The ADC12_A module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention.

6.9.14 CRC16

The CRC16 module produces a signature based on a sequence of entered data values and can be used for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.

6.9.15 REF Voltage Reference

The reference module (REF) is responsible for generation of all critical reference voltages that can be used by the various analog peripherals in the device.

6.9.16 Embedded Emulation Module (EEM) (L Version)

The EEM supports real-time in-system debugging. The L version of the EEM has the following features:

  • Eight hardware triggers or breakpoints on memory access
  • Two hardware triggers or breakpoints on CPU register write access
  • Up to ten hardware triggers can be combined to form complex triggers or breakpoints
  • Two cycle counters
  • Sequencer
  • State storage
  • Clock control on module level

6.9.17 Peripheral File Map

Table 6-11 lists the base address for the registers of each module.

Table 6-11 Peripheral Map

MODULE NAME BASE ADDRESS OFFSET ADDRESS RANGE
Special Functions (see Table 6-12) 0100h 000h-01Fh
PMM (see Table 6-13) 0120h 000h-010h
Flash Control (see Table 6-14) 0140h 000h-00Fh
CRC16 (see Table 6-15) 0150h 000h-007h
RAM Control (see Table 6-16) 0158h 000h-001h
Watchdog (see Table 6-17) 015Ch 000h-001h
UCS (see Table 6-18) 0160h 000h-01Fh
SYS (see Table 6-19) 0180h 000h-01Fh
Shared Reference (see Table 6-20) 01B0h 000h-001h
Port P1, P2 (see Table 6-21) 0200h 000h-01Fh
Port P3, P4 (see Table 6-22) 0220h 000h-00Bh
Port P5, P6 (see Table 6-23) 0240h 000h-00Bh
Port P7, P8 (see Table 6-24) 0260h 000h-00Bh
Port P9, P10 (see Table 6-25) 0280h 000h-00Bh
Port P11 (see Table 6-26) 02A0h 000h-00Ah
Port PJ (see Table 6-27) 0320h 000h-01Fh
TA0 (see Table 6-28) 0340h 000h-02Eh
TA1 (see Table 6-29) 0380h 000h-02Eh
TB0 (see Table 6-30) 03C0h 000h-02Eh
Real-Time Clock (RTC_A) (see Table 6-31) 04A0h 000h-01Bh
32-Bit Hardware Multiplier (see Table 6-32) 04C0h 000h-02Fh
DMA General Control (see Table 6-33) 0500h 000h-00Fh
DMA Channel 0 (see Table 6-33) 0510h 000h-00Ah
DMA Channel 1 (see Table 6-33) 0520h 000h-00Ah
DMA Channel 2 (see Table 6-33) 0530h 000h-00Ah
USCI_A0 (see Table 6-34) 05C0h 000h-01Fh
USCI_B0 (see Table 6-35) 05E0h 000h-01Fh
USCI_A1 (see Table 6-36) 0600h 000h-01Fh
USCI_B1 (see Table 6-37) 0620h 000h-01Fh
USCI_A2 (see Table 6-38) 0640h 000h-01Fh
USCI_B2 (see Table 6-39) 0660h 000h-01Fh
USCI_A3 (see Table 6-40) 0680h 000h-01Fh
USCI_B3 (see Table 6-41) 06A0h 000h-01Fh
ADC12_A (see Table 6-42) 0700h 000h-03Eh

Table 6-12 Special Function Registers (Base Address: 0100h)

REGISTER DESCRIPTION REGISTER OFFSET
SFR interrupt enable SFRIE1 00h
SFR interrupt flag SFRIFG1 02h
SFR reset pin control SFRRPCR 04h

Table 6-13 PMM Registers (Base Address: 0120h)

REGISTER DESCRIPTION REGISTER OFFSET
PMM Control 0 PMMCTL0 00h
PMM control 1 PMMCTL1 02h
SVS high side control SVSMHCTL 04h
SVS low side control SVSMLCTL 06h
PMM interrupt flags PMMIFG 0Ch
PMM interrupt enable PMMIE 0Eh
PMM power mode 5 control PM5CTL0 10h

Table 6-14 Flash Control Registers (Base Address: 0140h)

REGISTER DESCRIPTION REGISTER OFFSET
Flash control 1 FCTL1 00h
Flash control 3 FCTL3 04h
Flash control 4 FCTL4 06h

Table 6-15 CRC16 Registers (Base Address: 0150h)

REGISTER DESCRIPTION REGISTER OFFSET
CRC data input CRC16DI 00h
CRC data input reverse byte CRCDIRB 02h
CRC initialization and result CRCINIRES 04h
CRC result reverse byte CRCRESR 06h

Table 6-16 RAM Control Registers (Base Address: 0158h)

REGISTER DESCRIPTION REGISTER OFFSET
RAM control 0 RCCTL0 00h

Table 6-17 Watchdog Registers (Base Address: 015Ch)

REGISTER DESCRIPTION REGISTER OFFSET
Watchdog timer control WDTCTL 00h

Table 6-18 UCS Registers (Base Address: 0160h)

REGISTER DESCRIPTION REGISTER OFFSET
UCS control 0 UCSCTL0 00h
UCS control 1 UCSCTL1 02h
UCS control 2 UCSCTL2 04h
UCS control 3 UCSCTL3 06h
UCS control 4 UCSCTL4 08h
UCS control 5 UCSCTL5 0Ah
UCS control 6 UCSCTL6 0Ch
UCS control 7 UCSCTL7 0Eh
UCS control 8 UCSCTL8 10h

Table 6-19 SYS Registers (Base Address: 0180h)

REGISTER DESCRIPTION REGISTER OFFSET
System control SYSCTL 00h
Bootstrap loader configuration area SYSBSLC 02h
JTAG mailbox control SYSJMBC 06h
JTAG mailbox input 0 SYSJMBI0 08h
JTAG mailbox input 1 SYSJMBI1 0Ah
JTAG mailbox output 0 SYSJMBO0 0Ch
JTAG mailbox output 1 SYSJMBO1 0Eh
Bus Error vector generator SYSBERRIV 18h
User NMI vector generator SYSUNIV 1Ah
System NMI vector generator SYSSNIV 1Ch
Reset vector generator SYSRSTIV 1Eh

Table 6-20 Shared Reference Registers (Base Address: 01B0h)

REGISTER DESCRIPTION REGISTER OFFSET
Shared reference control REFCTL 00h

Table 6-21 Port P1, P2 Registers (Base Address: 0200h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P1 input P1IN 00h
Port P1 output P1OUT 02h
Port P1 direction P1DIR 04h
Port P1 pullup/pulldown enable P1REN 06h
Port P1 drive strength P1DS 08h
Port P1 selection P1SEL 0Ah
Port P1 interrupt vector word P1IV 0Eh
Port P1 interrupt edge select P1IES 18h
Port P1 interrupt enable P1IE 1Ah
Port P1 interrupt flag P1IFG 1Ch
Port P2 input P2IN 01h
Port P2 output P2OUT 03h
Port P2 direction P2DIR 05h
Port P2 pullup/pulldown enable P2REN 07h
Port P2 drive strength P2DS 09h
Port P2 selection P2SEL 0Bh
Port P2 interrupt vector word P2IV 1Eh
Port P2 interrupt edge select P2IES 19h
Port P2 interrupt enable P2IE 1Bh
Port P2 interrupt flag P2IFG 1Dh

Table 6-22 Port P3, P4 Registers (Base Address: 0220h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P3 input P3IN 00h
Port P3 output P3OUT 02h
Port P3 direction P3DIR 04h
Port P3 pullup/pulldown enable P3REN 06h
Port P3 drive strength P3DS 08h
Port P3 selection P3SEL 0Ah
Port P4 input P4IN 01h
Port P4 output P4OUT 03h
Port P4 direction P4DIR 05h
Port P4 pullup/pulldown enable P4REN 07h
Port P4 drive strength P4DS 09h
Port P4 selection P4SEL 0Bh

Table 6-23 Port P5, P6 Registers (Base Address: 0240h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P5 input P5IN 00h
Port P5 output P5OUT 02h
Port P5 direction P5DIR 04h
Port P5 pullup/pulldown enable P5REN 06h
Port P5 drive strength P5DS 08h
Port P5 selection P5SEL 0Ah
Port P6 input P6IN 01h
Port P6 output P6OUT 03h
Port P6 direction P6DIR 05h
Port P6 pullup/pulldown enable P6REN 07h
Port P6 drive strength P6DS 09h
Port P6 selection P6SEL 0Bh

Table 6-24 Port P7, P8 Registers (Base Address: 0260h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P7 input P7IN 00h
Port P7 output P7OUT 02h
Port P7 direction P7DIR 04h
Port P7 pullup/pulldown enable P7REN 06h
Port P7 drive strength P7DS 08h
Port P7 selection P7SEL 0Ah
Port P8 input P8IN 01h
Port P8 output P8OUT 03h
Port P8 direction P8DIR 05h
Port P8 pullup/pulldown enable P8REN 07h
Port P8 drive strength P8DS 09h
Port P8 selection P8SEL 0Bh

Table 6-25 Port P9, P10 Registers (Base Address: 0280h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P9 input P9IN 00h
Port P9 output P9OUT 02h
Port P9 direction P9DIR 04h
Port P9 pullup/pulldown enable P9REN 06h
Port P9 drive strength P9DS 08h
Port P9 selection P9SEL 0Ah
Port P10 input P10IN 01h
Port P10 output P10OUT 03h
Port P10 direction P10DIR 05h
Port P10 pullup/pulldown enable P10REN 07h
Port P10 drive strength P10DS 09h
Port P10 selection P10SEL 0Bh

Table 6-26 Port P11 Registers (Base Address: 02A0h)

REGISTER DESCRIPTION REGISTER OFFSET
Port P11 input P11IN 00h
Port P11 output P11OUT 02h
Port P11 direction P11DIR 04h
Port P11 pullup/pulldown enable P11REN 06h
Port P11 drive strength P11DS 08h
Port P11 selection P11SEL 0Ah

Table 6-27 Port J Registers (Base Address: 0320h)

REGISTER DESCRIPTION REGISTER OFFSET
Port PJ input PJIN 00h
Port PJ output PJOUT 02h
Port PJ direction PJDIR 04h
Port PJ pullup/pulldown enable PJREN 06h
Port PJ drive strength PJDS 08h

Table 6-28 TA0 Registers (Base Address: 0340h)

REGISTER DESCRIPTION REGISTER OFFSET
TA0 control TA0CTL 00h
Capture/compare control 0 TA0CCTL0 02h
Capture/compare control 1 TA0CCTL1 04h
Capture/compare control 2 TA0CCTL2 06h
Capture/compare control 3 TA0CCTL3 08h
Capture/compare control 4 TA0CCTL4 0Ah
TA0 counter register TA0R 10h
Capture/compare register 0 TA0CCR0 12h
Capture/compare register 1 TA0CCR1 14h
Capture/compare register 2 TA0CCR2 16h
Capture/compare register 3 TA0CCR3 18h
Capture/compare register 4 TA0CCR4 1Ah
TA0 expansion register 0 TA0EX0 20h
TA0 interrupt vector TA0IV 2Eh

Table 6-29 TA1 Registers (Base Address: 0380h)

REGISTER DESCRIPTION REGISTER OFFSET
TA1 control TA1CTL 00h
Capture/compare control 0 TA1CCTL0 02h
Capture/compare control 1 TA1CCTL1 04h
Capture/compare control 2 TA1CCTL2 06h
TA1 counter register TA1R 10h
Capture/compare register 0 TA1CCR0 12h
Capture/compare register 1 TA1CCR1 14h
Capture/compare register 2 TA1CCR2 16h
TA1 expansion register 0 TA1EX0 20h
TA1 interrupt vector TA1IV 2Eh

Table 6-30 TB0 Registers (Base Address: 03C0h)

REGISTER DESCRIPTION REGISTER OFFSET
TB0 control TB0CTL 00h
Capture/compare control 0 TB0CCTL0 02h
Capture/compare control 1 TB0CCTL1 04h
Capture/compare control 2 TB0CCTL2 06h
Capture/compare control 3 TB0CCTL3 08h
Capture/compare control 4 TB0CCTL4 0Ah
Capture/compare control 5 TB0CCTL5 0Ch
Capture/compare control 6 TB0CCTL6 0Eh
TB0 register TB0R 10h
Capture/compare register 0 TB0CCR0 12h
Capture/compare register 1 TB0CCR1 14h
Capture/compare register 2 TB0CCR2 16h
Capture/compare register 3 TB0CCR3 18h
Capture/compare register 4 TB0CCR4 1Ah
Capture/compare register 5 TB0CCR5 1Ch
Capture/compare register 6 TB0CCR6 1Eh
TB0 expansion register 0 TB0EX0 20h
TB0 interrupt vector TB0IV 2Eh

Table 6-31 Real-Time Clock Registers (Base Address: 04A0h)

REGISTER DESCRIPTION REGISTER OFFSET
RTC control 0 RTCCTL0 00h
RTC control 1 RTCCTL1 01h
RTC control 2 RTCCTL2 02h
RTC control 3 RTCCTL3 03h
RTC prescaler 0 control RTCPS0CTL 08h
RTC prescaler 1 control RTCPS1CTL 0Ah
RTC prescaler 0 RTCPS0 0Ch
RTC prescaler 1 RTCPS1 0Dh
RTC interrupt vector word RTCIV 0Eh
RTC seconds/counter register 1 RTCSEC/RTCNT1 10h
RTC minutes/counter register 2 RTCMIN/RTCNT2 11h
RTC hours/counter register 3 RTCHOUR/RTCNT3 12h
RTC day of week/counter register 4 RTCDOW/RTCNT4 13h
RTC days RTCDAY 14h
RTC month RTCMON 15h
RTC year low RTCYEARL 16h
RTC year high RTCYEARH 17h
RTC alarm minutes RTCAMIN 18h
RTC alarm hours RTCAHOUR 19h
RTC alarm day of week RTCADOW 1Ah
RTC alarm days RTCADAY 1Bh

Table 6-32 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)

REGISTER DESCRIPTION REGISTER OFFSET
16-bit operand 1 – multiply MPY 00h
16-bit operand 1 – signed multiply MPYS 02h
16-bit operand 1 – multiply accumulate MAC 04h
16-bit operand 1 – signed multiply accumulate MACS 06h
16-bit operand 2 OP2 08h
16 × 16 result low word RESLO 0Ah
16 × 16 result high word RESHI 0Ch
16 × 16 sum extension register SUMEXT 0Eh
32-bit operand 1 – multiply low word MPY32L 10h
32-bit operand 1 – multiply high word MPY32H 12h
32-bit operand 1 – signed multiply low word MPYS32L 14h
32-bit operand 1 – signed multiply high word MPYS32H 16h
32-bit operand 1 – multiply accumulate low word MAC32L 18h
32-bit operand 1 – multiply accumulate high word MAC32H 1Ah
32-bit operand 1 – signed multiply accumulate low word MACS32L 1Ch
32-bit operand 1 – signed multiply accumulate high word MACS32H 1Eh
32-bit operand 2 – low word OP2L 20h
32-bit operand 2 – high word OP2H 22h
32 × 32 result 0 – least significant word RES0 24h
32 × 32 result 1 RES1 26h
32 × 32 result 2 RES2 28h
32 × 32 result 3 – most significant word RES3 2Ah
MPY32 control register 0 MPY32CTL0 2Ch

Table 6-33 DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h)

REGISTER DESCRIPTION REGISTER OFFSET
DMA channel 0 control DMA0CTL 00h
DMA channel 0 source address low DMA0SAL 02h
DMA channel 0 source address high DMA0SAH 04h
DMA channel 0 destination address low DMA0DAL 06h
DMA channel 0 destination address high DMA0DAH 08h
DMA channel 0 transfer size DMA0SZ 0Ah
DMA channel 1 control DMA1CTL 00h
DMA channel 1 source address low DMA1SAL 02h
DMA channel 1 source address high DMA1SAH 04h
DMA channel 1 destination address low DMA1DAL 06h
DMA channel 1 destination address high DMA1DAH 08h
DMA channel 1 transfer size DMA1SZ 0Ah
DMA channel 2 control DMA2CTL 00h
DMA channel 2 source address low DMA2SAL 02h
DMA channel 2 source address high DMA2SAH 04h
DMA channel 2 destination address low DMA2DAL 06h
DMA channel 2 destination address high DMA2DAH 08h
DMA channel 2 transfer size DMA2SZ 0Ah
DMA module control 0 DMACTL0 00h
DMA module control 1 DMACTL1 02h
DMA module control 2 DMACTL2 04h
DMA module control 3 DMACTL3 06h
DMA module control 4 DMACTL4 08h
DMA interrupt vector DMAIV 0Eh

Table 6-34 USCI_A0 Registers (Base Address: 05C0h)

REGISTER DESCRIPTION REGISTER OFFSET
USCI control 1 UCA0CTL1 00h
USCI control 0 UCA0CTL0 01h
USCI baud rate 0 UCA0BR0 06h
USCI baud rate 1 UCA0BR1 07h
USCI modulation control UCA0MCTL 08h
USCI status UCA0STAT 0Ah
USCI receive buffer UCA0RXBUF 0Ch
USCI transmit buffer UCA0TXBUF 0Eh
USCI LIN control UCA0ABCTL 10h
USCI IrDA transmit control UCA0IRTCTL 12h
USCI IrDA receive control UCA0IRRCTL 13h
USCI interrupt enable UCA0IE 1Ch
USCI interrupt flags UCA0IFG 1Dh
USCI interrupt vector word UCA0IV 1Eh

Table 6-35 USCI_B0 Registers (Base Address: 05E0h)

REGISTER DESCRIPTION REGISTER OFFSET
USCI synchronous control 1 UCB0CTL1 00h
USCI synchronous control 0 UCB0CTL0 01h
USCI synchronous bit rate 0 UCB0BR0 06h
USCI synchronous bit rate 1 UCB0BR1 07h
USCI synchronous status UCB0STAT 0Ah
USCI synchronous receive buffer UCB0RXBUF 0Ch
USCI synchronous transmit buffer UCB0TXBUF 0Eh
USCI I2C own address UCB0I2COA 10h
USCI I2C slave address UCB0I2CSA 12h
USCI interrupt enable UCB0IE 1Ch
USCI interrupt flags UCB0IFG 1Dh
USCI interrupt vector word UCB0IV 1Eh

Table 6-36 USCI_A1 Registers (Base Address: 0600h)

REGISTER DESCRIPTION REGISTER OFFSET
USCI control 1 UCA1CTL1 00h
USCI control 0 UCA1CTL0 01h
USCI baud rate 0 UCA1BR0 06h
USCI baud rate 1 UCA1BR1 07h
USCI modulation control UCA1MCTL 08h
USCI status UCA1STAT 0Ah
USCI receive buffer UCA1RXBUF 0Ch
USCI transmit buffer UCA1TXBUF 0Eh
USCI LIN control UCA1ABCTL 10h
USCI IrDA transmit control UCA1IRTCTL 12h
USCI IrDA receive control UCA1IRRCTL 13h
USCI interrupt enable UCA1IE 1Ch
USCI interrupt flags UCA1IFG 1Dh
USCI interrupt vector word UCA1IV 1Eh

Table 6-37 USCI_B1 Registers (Base Address: 0620h)

REGISTER DESCRIPTION REGISTER OFFSET
USCI synchronous control 1 UCB1CTL1 00h
USCI synchronous control 0 UCB1CTL0 01h
USCI synchronous bit rate 0 UCB1BR0 06h
USCI synchronous bit rate 1 UCB1BR1 07h
USCI synchronous status UCB1STAT 0Ah
USCI synchronous receive buffer UCB1RXBUF 0Ch
USCI synchronous transmit buffer UCB1TXBUF 0Eh
USCI I2C own address UCB1I2COA 10h
USCI I2C slave address UCB1I2CSA 12h
USCI interrupt enable UCB1IE 1Ch
USCI interrupt flags UCB1IFG 1Dh
USCI interrupt vector word UCB1IV 1Eh

Table 6-38 USCI_A2 Registers (Base Address: 0640h)

REGISTER DESCRIPTION REGISTER OFFSET
USCI control 1 UCA2CTL1 00h
USCI control 0 UCA2CTL0 01h
USCI baud rate 0 UCA2BR0 06h
USCI baud rate 1 UCA2BR1 07h
USCI modulation control UCA2MCTL 08h
USCI status UCA2STAT 0Ah
USCI receive buffer UCA2RXBUF 0Ch
USCI transmit buffer UCA2TXBUF 0Eh
USCI LIN control UCA2ABCTL 10h
USCI IrDA transmit control UCA2IRTCTL 12h
USCI IrDA receive control UCA2IRRCTL 13h
USCI interrupt enable UCA2IE 1Ch
USCI interrupt flags UCA2IFG 1Dh
USCI interrupt vector word UCA2IV 1Eh

Table 6-39 USCI_B2 Registers (Base Address: 0660h)

REGISTER DESCRIPTION REGISTER OFFSET
USCI synchronous control 1 UCB2CTL1 00h
USCI synchronous control 0 UCB2CTL0 01h
USCI synchronous bit rate 0 UCB2BR0 06h
USCI synchronous bit rate 1 UCB2BR1 07h
USCI synchronous status UCB2STAT 0Ah
USCI synchronous receive buffer UCB2RXBUF 0Ch
USCI synchronous transmit buffer UCB2TXBUF 0Eh
USCI I2C own address UCB2I2COA 10h
USCI I2C slave address UCB2I2CSA 12h
USCI interrupt enable UCB2IE 1Ch
USCI interrupt flags UCB2IFG 1Dh
USCI interrupt vector word UCB2IV 1Eh

Table 6-40 USCI_A3 Registers (Base Address: 0680h)

REGISTER DESCRIPTION REGISTER OFFSET
USCI control 1 UCA3CTL1 00h
USCI control 0 UCA3CTL0 01h
USCI baud rate 0 UCA3BR0 06h
USCI baud rate 1 UCA3BR1 07h
USCI modulation control UCA3MCTL 08h
USCI status UCA3STAT 0Ah
USCI receive buffer UCA3RXBUF 0Ch
USCI transmit buffer UCA3TXBUF 0Eh
USCI LIN control UCA3ABCTL 10h
USCI IrDA transmit control UCA3IRTCTL 12h
USCI IrDA receive control UCA3IRRCTL 13h
USCI interrupt enable UCA3IE 1Ch
USCI interrupt flags UCA3IFG 1Dh
USCI interrupt vector word UCA3IV 1Eh

Table 6-41 USCI_B3 Registers (Base Address: 06A0h)

REGISTER DESCRIPTION REGISTER OFFSET
USCI synchronous control 1 UCB3CTL1 00h
USCI synchronous control 0 UCB3CTL0 01h
USCI synchronous bit rate 0 UCB3BR0 06h
USCI synchronous bit rate 1 UCB3BR1 07h
USCI synchronous status UCB3STAT 0Ah
USCI synchronous receive buffer UCB3RXBUF 0Ch
USCI synchronous transmit buffer UCB3TXBUF 0Eh
USCI I2C own address UCB3I2COA 10h
USCI I2C slave address UCB3I2CSA 12h
USCI interrupt enable UCB3IE 1Ch
USCI interrupt flags UCB3IFG 1Dh
USCI interrupt vector word UCB3IV 1Eh

Table 6-42 ADC12_A Registers (Base Address: 0700h)

REGISTER DESCRIPTION REGISTER OFFSET
Control register 0 ADC12CTL0 00h
Control register 1 ADC12CTL1 02h
Control register 2 ADC12CTL2 04h
Interrupt-flag register ADC12IFG 0Ah
Interrupt-enable register ADC12IE 0Ch
Interrupt-vector-word register ADC12IV 0Eh
ADC memory-control register 0 ADC12MCTL0 10h
ADC memory-control register 1 ADC12MCTL1 11h
ADC memory-control register 2 ADC12MCTL2 12h
ADC memory-control register 3 ADC12MCTL3 13h
ADC memory-control register 4 ADC12MCTL4 14h
ADC memory-control register 5 ADC12MCTL5 15h
ADC memory-control register 6 ADC12MCTL6 16h
ADC memory-control register 7 ADC12MCTL7 17h
ADC memory-control register 8 ADC12MCTL8 18h
ADC memory-control register 9 ADC12MCTL9 19h
ADC memory-control register 10 ADC12MCTL10 1Ah
ADC memory-control register 11 ADC12MCTL11 1Bh
ADC memory-control register 12 ADC12MCTL12 1Ch
ADC memory-control register 13 ADC12MCTL13 1Dh
ADC memory-control register 14 ADC12MCTL14 1Eh
ADC memory-control register 15 ADC12MCTL15 1Fh
Conversion memory 0 ADC12MEM0 20h
Conversion memory 1 ADC12MEM1 22h
Conversion memory 2 ADC12MEM2 24h
Conversion memory 3 ADC12MEM3 26h
Conversion memory 4 ADC12MEM4 28h
Conversion memory 5 ADC12MEM5 2Ah
Conversion memory 6 ADC12MEM6 2Ch
Conversion memory 7 ADC12MEM7 2Eh
Conversion memory 8 ADC12MEM8 30h
Conversion memory 9 ADC12MEM9 32h
Conversion memory 10 ADC12MEM10 34h
Conversion memory 11 ADC12MEM11 36h
Conversion memory 12 ADC12MEM12 38h
Conversion memory 13 ADC12MEM13 3Ah
Conversion memory 14 ADC12MEM14 3Ch
Conversion memory 15 ADC12MEM15 3Eh

6.10 Input/Output Schematics

6.10.1 Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger

MSP430BT5190 slas703-020.gif

Table 6-43 Port P1 (P1.0 to P1.7) Pin Functions

PIN NAME (P1.x) x FUNCTION CONTROL BITS OR SIGNALS
P1DIR.x P1SEL.x
P1.0/TA0CLK/ACLK 0 P1.0 (I/O) I: 0; O: 1 0
TA0.TA0CLK 0 1
ACLK 1 1
P1.1/TA0.0 1 P1.1 (I/O) I: 0; O: 1 0
TA0.CCI0A 0 1
TA0.0 1 1
P1.2/TA0.1 2 P1.2 (I/O) I: 0; O: 1 0
TA0.CCI1A 0 1
TA0.1 1 1
P1.3/TA0.2 3 P1.3 (I/O) I: 0; O: 1 0
TA0.CCI2A 0 1
TA0.2 1 1
P1.4/TA0.3 4 P1.4 (I/O) I: 0; O: 1 0
TA0.CCI3A 0 1
TA0.3 1 1
P1.5/TA0.4 5 P1.5 (I/O) I: 0; O: 1 0
TA0.CCI4A 0 1
TA0.4 1 1
P1.6/SMCLK 6 P1.6 (I/O) I: 0; O: 1 0
SMCLK 1 1
P1.7 7 P1.7 (I/O) I: 0; O: 1 0

6.10.2 Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger

MSP430BT5190 slas703-021.gif

Table 6-44 Port P2 (P2.0 to P2.7) Pin Functions

PIN NAME (P2.x) x FUNCTION CONTROL BITS OR SIGNALS
P2DIR.x P2SEL.x
P2.0/TA1CLK/MCLK 0 P2.0 (I/O) I: 0; O: 1 0
TA1CLK 0 1
MCLK 1 1
P2.1/TA1.0 1 P2.1 (I/O) I: 0; O: 1 0
TA1.CCI0A 0 1
TA1.0 1 1
P2.2/TA1.1 2 P2.2 (I/O) I: 0; O: 1 0
TA1.CCI1A 0 1
TA1.1 1 1
P2.3/TA1.2 3 P2.3 (I/O) I: 0; O: 1 0
TA1.CCI2A 0 1
TA1.2 1 1
P2.4/RTCCLK 4 P2.4 (I/O) I: 0; O: 1 0
RTCCLK 1 1
P2.5 5 P2.5 (I/O I: 0; O: 1 0
P2.6/ACLK 6 P2.6 (I/O) I: 0; O: 1 0
ACLK 1 1
P2.7/ADC12CLK/DMAE0 7 P2.7 (I/O) I: 0; O: 1 0
DMAE0 0 1
ADC12CLK 1 1

6.10.3 Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger

MSP430BT5190 slas703-022.gif

Table 6-45 Port P3 (P3.0 to P3.7) Pin Functions

PIN NAME (P3.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P3DIR.x P3SEL.x
P3.0/UCB0STE/UCA0CLK 0 P3.0 (I/O) I: 0; O: 1 0
UCB0STE/UCA0CLK(2)(4) X 1
P3.1/UCB0SIMO/UCB0SDA 1 P3.1 (I/O) I: 0; O: 1 0
UCB0SIMO/UCB0SDA(2)(3) X 1
P3.2/UCB0SOMI/UCB0SCL 2 P3.2 (I/O) I: 0; O: 1 0
UCB0SOMI/UCB0SCL(2)(3) X 1
P3.3/UCB0CLK/UCA0STE 3 P3.3 (I/O) I: 0; O: 1 0
UCB0CLK/UCA0STE(2) X 1
P3.4/UCA0TXD/UCA0SIMO 4 P3.4 (I/O) I: 0; O: 1 0
UCA0TXD/UCA0SIMO(2) X 1
P3.5/UCA0RXD/UCA0SOMI 5 P3.5 (I/O) I: 0; O: 1 0
UCA0RXD/UCA0SOMI(2) X 1
P3.6/UCB1STE/UCA1CLK 6 P3.6 (I/O) I: 0; O: 1 0
UCB1STE/UCA1CLK(2)(5) X 1
P3.7/UCB1SIMO/UCB1SDA 7 P3.7 (I/O) I: 0; O: 1 0
UCB1SIMO/UCB1SDA(2)(3) X 1
(1) X = Don't care
(2) The pin direction is controlled by the USCI module.
(3) If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
(4) UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI B0 is forced to 3-wire SPI mode if 4-wire SPI mode is selected.
(5) UCA1CLK function takes precedence over UCB1STE function. If the pin is required as UCA1CLK input or output, USCI B1 is forced to 3-wire SPI mode if 4-wire SPI mode is selected.

6.10.4 Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger

MSP430BT5190 slas703-023.gif

Table 6-46 Port P4 (P4.0 to P4.7) Pin Functions

PIN NAME (P4.x) x FUNCTION CONTROL BITS OR SIGNALS
P4DIR.x P4SEL.x
P4.0/TB0.0 0 4.0 (I/O) I: 0; O: 1 0
TB0.CCI0A and TB0.CCI0B 0 1
TB0.0(1) 1 1
P4.1/TB0.1 1 4.1 (I/O) I: 0; O: 1 0
TB0.CCI1A and TB0.CCI1B 0 1
TB0.1(1) 1 1
P4.2/TB0.2 2 4.2 (I/O) I: 0; O: 1 0
TB0.CCI2A and TB0.CCI2B 0 1
TB0.2(1) 1 1
P4.3/TB0.3 3 4.3 (I/O) I: 0; O: 1 0
TB0.CCI3A and TB0.CCI3B 0 1
TB0.3(1) 1 1
P4.4/TB0.5 4 4.4 (I/O) I: 0; O: 1 0
TB0.CCI4A and TB0.CCI4B 0 1
TB0.4(1) 1 1
P4.5/TB0.5 5 4.5 (I/O) I: 0; O: 1 0
TB0.CCI5A and TB0.CCI5B 0 1
TB0.5(1) 1 1
P4.6/TB0.6 6 4.6 (I/O) I: 0; O: 1 0
TB0.CCI6A and TB0.CCI6B 0 1
TB0.6(1) 1 1
P4.7/TB0CLK/SMCLK 7 4.7 (I/O) I: 0; O: 1 0
TB0CLK 0 1
SMCLK 1 1
(1) Setting TBOUTH causes all Timer_B configured outputs to be set to high impedance.

6.10.5 Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger

MSP430BT5190 slas703-024.gif

Table 6-47 Port P5 (P5.0 and P5.1) Pin Functions

PIN NAME (P5.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P5DIR.x P5SEL.x REFOUT
P5.0/A8/VREF+/VeREF+ 0 P5.0 (I/O)(2) I: 0; O: 1 0 X
A8/VeREF+(3) X 1 0
A8/VREF+(4) X 1 1
P5.1/A9/VREF–/VeREF– 1 P5.1 (I/O)(2) I: 0; O: 1 0 X
A9/VeREF–(5) X 1 0
A9/VREF–(6) X 1 1
(1) X = Don't care
(2) Default condition
(3) Setting the P5SEL.0 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. An external voltage can be applied to VeREF+ and used as the reference for the ADC12_A. Channel A8, when selected with the INCHx bits, is connected to the VREF+/VeREF+ pin.
(4) Setting the P5SEL.0 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. The ADC12_A, VREF+ reference is available at the pin. Channel A8, when selected with the INCHx bits, is connected to the VREF+/VeREF+ pin.
(5) Setting the P5SEL.1 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. An external voltage can be applied to VeREF- and used as the reference for the ADC12_A. Channel A9, when selected with the INCHx bits, is connected to the VREF-/VeREF- pin.
(6) Setting the P5SEL.1 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. The ADC12_A, VREF– reference is available at the pin. Channel A9, when selected with the INCHx bits, is connected to the VREF-/VeREF- pin.

6.10.6 Port P5, P5.2, Input/Output With Schmitt Trigger

MSP430BT5190 slas703-025.gif

6.10.7 Port P5, P5.3, Input/Output With Schmitt Trigger

MSP430BT5190 slas703_p5_3.gif

Table 6-48 Port P5 (P5.2 and P5.3) Pin Functions

PIN NAME (P5.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P5DIR.x P5SEL.2 P5SEL.3 XT2BYPASS
P5.2/XT2IN 2 P5.2 (I/O) I: 0; O: 1 0 X X
XT2IN crystal mode(2) X 1 X 0
XT2IN bypass mode(2) X 1 X 1
P5.3/XT2OUT 3 P5.3 (I/O) I: 0; O: 1 0 0 X
XT2OUT crystal mode(3) X 1 X 0
P5.3 (I/O)(3) X 1 0 1
(1) X = Don't care
(2) Setting P5SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P5.2 is configured for crystal mode or bypass mode.
(3) Setting P5SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.3 can be used as general-purpose I/O.

6.10.8 Port P5, P5.4 to P5.7, Input/Output With Schmitt Trigger

MSP430BT5190 slas703-027.gif

Table 6-49 Port P5 (P5.4 to P5.7) Pin Functions

PIN NAME (P5.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P5DIR.x P5SEL.x
P5.4/UCB1SOMI/UCB1SCL 4 P5.4 (I/O) I: 0; O: 1 0
UCB1SOMI/UCB1SCL(2)(3) X 1
P5.5/UCB1CLK/UCA1STE 5 P5.5 (I/O) I: 0; O: 1 0
UCB1CLK/UCA1STE(2)(4) X 1
P5.6/UCA1TXD/UCA1SIMO 6 P5.6 (I/O) I: 0; O: 1 0
UCA1TXD/UCA1SIMO(2) X 1
P5.7/UCA1RXD/UCA1SOMI 7 P5.7 (I/O) I: 0; O: 1 0
UCA1RXD/UCA1SOMI(2) X 1
(1) X = Don't care
(2) The pin direction is controlled by the USCI module.
(3) If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
(4) UCB1CLK function takes precedence over UCA1STE function. If the pin is required as UCB1CLK input or output, USCI A1 is forced to 3-wire SPI mode if 4-wire SPI mode is selected.

6.10.9 Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger

MSP430BT5190 slas703-028.gif

Table 6-50 Port P6 (P6.0 to P6.7) Pin Functions

PIN NAME (P6.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P6DIR.x P6SEL.x INCHx
P6.0/A0 0 P6.0 (I/O) I: 0; O: 1 0 X
A0(2)(3) X X 0
P6.1/A1 1 P6.1 (I/O) I: 0; O: 1 0 X
A1(2)(3) X X 1
P6.2/A2 2 P6.2 (I/O) I: 0; O: 1 0 X
A2(2)(3) X X 2
P6.3/A3 3 P6.3 (I/O) I: 0; O: 1 0 X
A3(2)(3) X X 3
P6.4/A4 4 P6.4 (I/O) I: 0; O: 1 0 X
A4(2)(3) X X 4
P6.5/A5 5 P6.5 (I/O) I: 0; O: 1 0 X
A5(1)(2)(3) X X 5
P6.6/A6 6 P6.6 (I/O) I: 0; O: 1 0 X
A6(2)(3) X X 6
P6.7/A7 7 P6.7 (I/O) I: 0; O: 1 0 X
A7(2)(3) X X 7
(1) X = Don't care
(2) Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals.
(3) The ADC12_A channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.

6.10.10 Port P7, P7.0, Input/Output With Schmitt Trigger

MSP430BT5190 slas703-029.gif

6.10.11 Port P7, P7.1, Input/Output With Schmitt Trigger

MSP430BT5190 slas703_p7_1.gif

Table 6-51 Port P7 (P7.0 and P7.1) Pin Functions

PIN NAME (P7.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P7DIR.x P7SEL.0 P7SEL.1 XT1BYPASS
P7.0/XIN 0 P7.0 (I/O) I: 0; O: 1 0 X X
XIN crystal mode(2) X 1 X 0
XIN bypass mode(2) X 1 X 1
P7.1/XOUT 1 P7.1 (I/O) I: 0; O: 1 0 0 X
XOUT crystal mode(3) X 1 X 0
P7.1 (I/O)(3) X 1 0 1
(1) X = Don't care
(2) Setting P7SEL.0 causes the general-purpose I/O to be disabled. Pending the setting of XT1BYPASS, P7.0 is configured for crystal mode or bypass mode.
(3) Setting P7SEL.0 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P7.1 can be used as general-purpose I/O.

6.10.12 Port P7, P7.2 and P7.3, Input/Output With Schmitt Trigger

MSP430BT5190 slas703-031.gif

Table 6-52 Port P7 (P7.2 and P7.3) Pin Functions

PIN NAME (P7.x) x FUNCTION CONTROL BITS OR SIGNALS
P7DIR.x P7SEL.x
P7.2/TB0OUTH/SVMOUT 2 P7.2 (I/O) I: 0; O: 1 0
TB0OUTH 0 1
SVMOUT 1 1
P7.3/TA1.2 3 P7.3 (I/O) I: 0; O: 1 0
TA1.CCI2B 0 1
TA1.2 1 1

6.10.13 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger

MSP430BT5190 slas703-032.gif

Table 6-53 Port P7 (P7.4 to P7.7) Pin Functions

PIN NAME (P7.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P7DIR.x P7SEL.x INCHx
P7.4/A12 4 P7.4 (I/O) I: 0; O: 1 0 X
A12(2)(3) X X 12
P7.5/A13 5 P7.5 (I/O) I: 0; O: 1 0 X
A13(2)(3) X X 13
P7.6/A14 6 P7.6 (I/O) I: 0; O: 1 0 X
A14(2)(3) X X 14
P7.7/A15 7 P7.7 (I/O) I: 0; O: 1 0 X
A15(2)(3) X X 15
(1) X = Don't care
(2) Setting the P7SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals.
(3) The ADC12_A channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.

6.10.14 Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger

MSP430BT5190 slas703-033.gif

Table 6-54 Port P8 (P8.0 to P8.7) Pin Functions

PIN NAME (P8.x) x FUNCTION CONTROL BITS OR SIGNALS
P8DIR.x P8SEL.x
P8.0/TA0.0 0 P8.0 (I/O) I: 0; O: 1 0
TA0.CCI0B 0 1
TA0.0 1 1
P8.1/TA0.1 1 P8.1 (I/O) I: 0; O: 1 0
TA0.CCI1B 0 1
TA0.1 1 1
P8.2/TA0.2 2 P8.2 (I/O) I: 0; O: 1 0
TA0.CCI2B 0 1
TA0.2 1 1
P8.3/TA0.3 3 P8.3 (I/O) I: 0; O: 1 0
TA0.CCI3B 0 1
TA0.3 1 1
P8.4/TA0.4 4 P8.4 (I/O) I: 0; O: 1 0
TA0.CCI4B 0 1
TA0.4 1 1
P8.5/TA1.0 5 P8.5 (I/O) I: 0; O: 1 0
TA1.CCI0B 0 1
TA1.0 1 1
P8.6/TA1.1 6 P8.6 (I/O) I: 0; O: 1 0
TA1.CCI1B 0 1
TA1.1 1 1
P8.7 7 P8.7 (I/O) I: 0; O: 1 0

6.10.15 Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger

MSP430BT5190 slas703-034.gif

Table 6-55 Port P9 (P9.0 to P9.7) Pin Functions

PIN NAME (P9.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P9DIR.x P9SEL.x
P9.0/UCB2STE/UCA2CLK 0 P9.0 (I/O) I: 0; O: 1 0
UCB2STE/UCA2CLK(2)(4) X 1
P9.1/UCB2SIMO/UCB2SDA 1 P9.1 (I/O) I: 0; O: 1 0
UCB2SIMO/UCB2SDA(2)(3) X 1
P9.2/UCB2SOMI/UCB2SCL 2 P9.2 (I/O) I: 0; O: 1 0
UCB2SOMI/UCB2SCL(2)(3) X 1
P9.3/UCB2CLK/UCA2STE 3 P9.3 (I/O) I: 0; O: 1 0
UCB2CLK/UCA2STE(2)(5) X 1
P9.4/UCA2TXD/UCA2SIMO 4 P9.4 (I/O) I: 0; O: 1 0
UCA2TXD/UCA2SIMO(2) X 1
P9.5/UCA2RXD/UCA2SOMI 5 P9.5 (I/O) I: 0; O: 1 0
UCA2RXD/UCA2SOMI(2) X 1
P9.6 6 P9.6 (I/O) I: 0; O: 1 0
P9.7 7 P9.7 (I/O) I: 0; O: 1 0
(1) X = Don't care
(2) The pin direction is controlled by the USCI module.
(3) If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
(4) UCA2CLK function takes precedence over UCB2STE function. If the pin is required as UCA2CLK input or output, USCI B2 is forced to 3-wire SPI mode if 4-wire SPI mode is selected.
(5) UCB2CLK function takes precedence over UCA2STE function. If the pin is required as UCB2CLK input or output, USCI A2 is forced to 3-wire SPI mode if 4-wire SPI mode is selected.

6.10.16 Port P10, P10.0 to P10.7, Input/Output With Schmitt Trigger

MSP430BT5190 slas703-035.gif

Table 6-56 Port P10 (P10.0 to P10.7) Pin Functions

PIN NAME (P10.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P10DIR.x P10SEL.x
P10.0/UCB3STE/UCA3CLK 0 P10.0 (I/O) I: 0; O: 1 0
UCB3STE/UCA3CLK(2)(4) X 1
P10.1/UCB3SIMO/UCB3SDA 1 P10.1 (I/O) I: 0; O: 1 0
UCB3SIMO/UCB3SDA(2)(3) X 1
P10.2/UCB3SOMI/UCB3SCL 2 P10.2 (I/O) I: 0; O: 1 0
UCB3SOMI/UCB3SCL(2)(3) X 1
P10.3/UCB3CLK/UCA3STE 3 P10.3 (I/O) I: 0; O: 1 0
UCB3CLK/UCA3STE(2) X 1
P10.4/UCA3TXD/UCA3SIMO 4 P10.4 (I/O) I: 0; O: 1 0
UCA3TXD/UCA3SIMO(2) X 1
P10.5/UCA3RXD/UCA3SOMI 5 P10.5 (I/O) I: 0; O: 1 0
UCA3RXD/UCA3SOMI(2) X 1
P10.6 6 P10.6 (I/O) I: 0; O: 1 0
Reserved(5) X 1
P10.7 7 P10.7 (I/O) I: 0; O: 1 0
Reserved(5) x 1
(1) X = Don't care
(2) The pin direction is controlled by the USCI module.
(3) If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
(4) UCA3CLK function takes precedence over UCB3STE function. If the pin is required as UCA3CLK input or output, USCI B3 is forced to 3-wire SPI mode if 4-wire SPI mode is selected.
(5) The secondary function on these pins are reserved for factory test purposes. Application should keep the P10SEL.x of these ports cleared to prevent potential conflicts with the application.

6.10.17 Port P11, P11.0 to P11.2, Input/Output With Schmitt Trigger

MSP430BT5190 slas703-036.gif

Table 6-57 Port P11 (P11.0 to P11.2) Pin Functions

PIN NAME (P11.x) x FUNCTION CONTROL BITS OR SIGNALS
P11DIR.x P11SEL.x
P11.0/ACLK 0 P11.0 (I/O) I: 0; O: 1 0
ACLK 1 1
P11.1/MCLK 1 P11.1 (I/O) I: 0; O: 1 0
MCLK 1 1
P11.2/SMCLK 2 P11.2 (I/O) I: 0; O: 1 0
SMCLK 1 1

6.10.18 Port J, J.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output

MSP430BT5190 slas703-037.gif

6.10.19 Port J, J.1 to J.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output

MSP430BT5190 slas703-038.gif

Table 6-58 Port PJ (PJ.0 to PJ.3) Pin Functions

PIN NAME (PJ.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
PJDIR.x
PJ.0/TDO 0 PJ.0 (I/O)(2) I: 0; O: 1
TDO(3) X
PJ.1/TDI/TCLK 1 PJ.1 (I/O)(2) I: 0; O: 1
TDI/TCLK(3)(4) X
PJ.2/TMS 2 PJ.2 (I/O)(2) I: 0; O: 1
TMS(3)(4) X
PJ.3/TCK 3 PJ.3 (I/O)(2) I: 0; O: 1
TCK(3)(4) X
(1) X = Don't care
(2) Default condition
(3) The pin direction is controlled by the JTAG module.
(4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care.

6.11 Device Descriptors (TLV)

Table 6-59 shows the complete contents of the device descriptor tag-length-value (TLV) structure.

Table 6-59 Device Descriptor Table(1)

DESCRIPTION ADDRESS SIZE
(bytes)
MSP430BT5190
VALUE
Info Block Info length 01A00h 1 06h
CRC length 01A01h 1 06h
CRC value 01A02h 2 per unit
Device ID 01A04h 1 05h
Device ID 01A05h 1 80h
Hardware revision 01A06h 1 per unit
Firmware revision 01A07h 1 per unit
Die Record Die Record Tag 01A08h 1 08h
Die Record length 01A09h 1 0Ah
Lot/Wafer ID 01A0Ah 4 per unit
Die X position 01A0Eh 2 per unit
Die Y position 01A10h 2 per unit
Test results 01A12h 2 per unit
ADC12 Calibration ADC12 Calibration Tag 01A14h 1 11h
ADC12 Calibration length 01A15h 1 10h
ADC Gain Factor 01A16h 2 per unit
ADC Offset 01A18h 2 per unit
ADC 1.5-V Reference
Temp. Sensor 30°C
01A1Ah 2 per unit
ADC 1.5-V Reference
Temp. Sensor 85°C
01A1Ch 2 per unit
ADC 2.0-V Reference
Temp. Sensor 30°C
01A1Eh 2 per unit
ADC 2.0-V Reference
Temp. Sensor 85°C
01A20h 2 per unit
ADC 2.5-V Reference
Temp. Sensor 30°C
01A22h 2 per unit
ADC 2.5-V Reference
Temp. Sensor 85°C
01A24h 2 per unit
REF Calibration REF Calibration Tag 01A26h 1 12h
REF Calibration length 01A27h 1 06h
REF 1.5-V Reference 01A28h 2 per unit
REF 2.0-V Reference 01A2Ah 2 per unit
REF 2.5-V Reference 01A2Ch 2 per unit
Peripheral Descriptor Peripheral Descriptor Tag 01A2Eh 1 02h
Peripheral Descriptor Length 01A2Fh 1 61h
Memory 1 2 08h
8Ah
Memory 2 2 0Ch
86h
Memory 3 2 0Eh
30h
Memory 4 2 2Eh
98h
Memory 5 0/1 NA
Delimiter 1 00h
Peripheral count 1 21h
MSP430CPUXV2 2 00h
23h
SBW 2 00h
0Fh
EEM-8 2 00h
05h
TI BSL 2 00h
FCh
Package 2 00h
1Fh
SFR 2 10h
41h
PMM 2 02h
30h
FCTL 2 02h
38h
CRC16-straight 2 01h
3Ch
CRC16-bit reversed 2 00h
3Dh
RAMCTL 2 00h
44h
WDT_A 2 00h
40h
UCS 2 01h
48h
SYS 2 02h
42h
REF 2 03h
A0h
Port 1/2 2 05h
51h
Port 3/4 2 02h
52h
Port 5/6 2 02h
53h
Port 7/8 2 02h
54h
Port 9/10 2 02h
55h
Port 11/12 2 02h
56h
JTAG 2 08h
5Fh
TA0 2 02h
62h
TA1 2 04h
61h
TB0 2 04h
67h
RTC 2 0Eh
68h
MPY32 2 02h
85h
DMA-3 2 04h
47h
USCI_A/B 2 0Ch
90h
USCI_A/B 2 04h
90h
USCI_A/B 2 04h
90h
USCI_A/B 2 04h
90h
ADC12_A 2 08h
D1h
Interrupts TB0.CCIFG0 1 64h
TB0.CCIFG1..6 1 65h
WDTIFG 1 40h
USCI_A0 1 90h
USCI_B0 1 91h
ADC12_A 1 D0h
TA0.CCIFG0 1 60h
TA0.CCIFG1..4 1 61h
USCI_A2 1 94h
USCI_B2 1 95h
DMA 1 46h
TA1.CCIFG0 1 62h
TA1.CCIFG1..2 1 63h
P1 1 50h
USCI_A1 1 92h
USCI_B1 1 93h
USCI_A3 1 96h
USCI_B3 1 97h
P2 1 51h
RTC_A 1 68h
Delimiter 1 00h
(1) NA = Not applicable