SLAS703B April   2010  – August 2015 MSP430BT5190

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Characteristics
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Thermal Characteristics
    7. 5.7  Schmitt-Trigger Inputs - General-Purpose I/O
    8. 5.8  Inputs - Ports P1 and P2
    9. 5.9  Leakage Current - General-Purpose I/O
    10. 5.10 Outputs - General-Purpose I/O (Full Drive Strength)
    11. 5.11 Outputs - General-Purpose I/O (Reduced Drive Strength)
    12. 5.12 Output Frequency - General-Purpose I/O
    13. 5.13 Typical Characteristics - Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 5.14 Typical Characteristics - Outputs, Full Drive Strength (PxDS.y = 1)
    15. 5.15 Crystal Oscillator, XT1, Low-Frequency Mode
    16. 5.16 Crystal Oscillator, XT1, High-Frequency Mode
    17. 5.17 Crystal Oscillator, XT2
    18. 5.18 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    19. 5.19 Internal Reference, Low-Frequency Oscillator (REFO)
    20. 5.20 DCO Frequency
    21. 5.21 PMM, Brown-Out Reset (BOR)
    22. 5.22 PMM, Core Voltage
    23. 5.23 PMM, SVS High Side
    24. 5.24 PMM, SVM High Side
    25. 5.25 PMM, SVS Low Side
    26. 5.26 PMM, SVM Low Side
    27. 5.27 Wake-up Times From Low-Power Modes and Reset
    28. 5.28 Timer_A
    29. 5.29 Timer_B
    30. 5.30 USCI (UART Mode), Recommended Operating Conditions
    31. 5.31 USCI (UART Mode)
    32. 5.32 USCI (SPI Master Mode), Recommended Operating Conditions
    33. 5.33 USCI (SPI Master Mode)
    34. 5.34 USCI (SPI Slave Mode)
    35. 5.35 USCI (I2C Mode)
    36. 5.36 12-Bit ADC, Power Supply and Input Range Conditions
    37. 5.37 12-Bit ADC, Timing Parameters
    38. 5.38 12-Bit ADC, Linearity Parameters
    39. 5.39 12-Bit ADC, Temperature Sensor and Built-In VMID
    40. 5.40 REF, External Reference
    41. 5.41 REF, Built-In Reference
    42. 5.42 Flash Memory
    43. 5.43 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Operating Modes
    3. 6.3  Interrupt Vector Addresses
    4. 6.4  Memory Organization
    5. 6.5  Bootstrap Loader (BSL)
    6. 6.6  JTAG Operation
      1. 6.6.1 JTAG Standard Interface
      2. 6.6.2 Spy-Bi-Wire Interface
    7. 6.7  Flash Memory
    8. 6.8  RAM
    9. 6.9  Peripherals
      1. 6.9.1  Digital I/O
      2. 6.9.2  Oscillator and System Clock
      3. 6.9.3  Power-Management Module (PMM)
      4. 6.9.4  Hardware Multiplier (MPY)
      5. 6.9.5  Real-Time Clock (RTC_A)
      6. 6.9.6  Watchdog Timer (WDT_A)
      7. 6.9.7  System Module (SYS)
      8. 6.9.8  DMA Controller
      9. 6.9.9  Universal Serial Communication Interface (USCI)
      10. 6.9.10 TA0
      11. 6.9.11 TA1
      12. 6.9.12 TB0
      13. 6.9.13 ADC12_A
      14. 6.9.14 CRC16
      15. 6.9.15 REF Voltage Reference
      16. 6.9.16 Embedded Emulation Module (EEM) (L Version)
      17. 6.9.17 Peripheral File Map
    10. 6.10 Input/Output Schematics
      1. 6.10.1  Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
      2. 6.10.2  Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger
      3. 6.10.3  Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger
      4. 6.10.4  Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
      5. 6.10.5  Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
      6. 6.10.6  Port P5, P5.2, Input/Output With Schmitt Trigger
      7. 6.10.7  Port P5, P5.3, Input/Output With Schmitt Trigger
      8. 6.10.8  Port P5, P5.4 to P5.7, Input/Output With Schmitt Trigger
      9. 6.10.9  Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger
      10. 6.10.10 Port P7, P7.0, Input/Output With Schmitt Trigger
      11. 6.10.11 Port P7, P7.1, Input/Output With Schmitt Trigger
      12. 6.10.12 Port P7, P7.2 and P7.3, Input/Output With Schmitt Trigger
      13. 6.10.13 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger
      14. 6.10.14 Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger
      15. 6.10.15 Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger
      16. 6.10.16 Port P10, P10.0 to P10.7, Input/Output With Schmitt Trigger
      17. 6.10.17 Port P11, P11.0 to P11.2, Input/Output With Schmitt Trigger
      18. 6.10.18 Port J, J.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      19. 6.10.19 Port J, J.1 to J.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    11. 6.11 Device Descriptors (TLV)
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Getting Started and Next Steps
      2. 7.1.2 Development Tools Support
        1. 7.1.2.1 Hardware Features
        2. 7.1.2.2 Recommended Hardware Options
          1. 7.1.2.2.1 Experimenter Boards
          2. 7.1.2.2.2 Debugging and Programming Tools
          3. 7.1.2.2.3 Production Programmers
        3. 7.1.2.3 Recommended Software Options
          1. 7.1.2.3.1 Integrated Development Environments
          2. 7.1.2.3.2 MSP430Ware
          3. 7.1.2.3.3 TI-RTOS
          4. 7.1.2.3.4 Command-Line Programmer
      3. 7.1.3 Device and Development Tool Nomenclature
    2. 7.2 Documentation Support
    3. 7.3 Community Resources
    4. 7.4 Trademarks
    5. 7.5 Electrostatic Discharge Caution
    6. 7.6 Export Control Notice
    7. 7.7 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Terminal Configuration and Functions

4.1 Pin Diagrams

Figure 4-1 shows the pinout of the 100-pin PZ package.

MSP430BT5190 pinout_pz100_slas703.gifFigure 4-1 100-Pin PZ Package (Top View)

Figure 4-2 shows the pinout of the 113-pin ZQW package.

MSP430BT5190 pinout_zqw113_slas703.gifFigure 4-2 113-Pin ZQW Package (Top View)

4.2 Signal Descriptions

Table 4-1 describes the signals.

Table 4-1 Terminal Functions

TERMINAL I/O(1) DESCRIPTION
NAME NO.
PZ ZQW
P6.4/A4 1 A1 I/O General-purpose digital I/O
Analog input A4 – ADC
P6.5/A5 2 E4 I/O General-purpose digital I/O
Analog input A5 – ADC
P6.6/A6 3 B1 I/O General-purpose digital I/O
Analog input A6 – ADC
P6.7/A7 4 C2 I/O General-purpose digital I/O
Analog input A7 – ADC
P7.4/A12 5 F4 I/O General-purpose digital I/O
Analog input A12 –ADC
P7.5/A13 6 C1 I/O General-purpose digital I/O
Analog input A13 – ADC
P7.6/A14 7 D2 I/O General-purpose digital I/O
Analog input A14 – ADC
P7.7/A15 8 G4 I/O General-purpose digital I/O
Analog input A15 – ADC
P5.0/A8/VREF+/VeREF+ 9 D1 I/O General-purpose digital I/O
Analog input A8 – ADC
Output of reference voltage to the ADC
Input for an external reference voltage to the ADC
P5.1/A9/VREF-/VeREF- 10 E1 I/O General-purpose digital I/O
Analog input A9 – ADC
Negative terminal for the ADC reference voltage for both sources, the internal reference voltage, or an external applied reference voltage
AVCC 11 E2 Analog power supply
AVSS 12 F2 Analog ground supply
P7.0/XIN 13 F1 I/O General-purpose digital I/O
Input terminal for crystal oscillator XT1
P7.1/XOUT 14 G1 I/O General-purpose digital I/O
Output terminal of crystal oscillator XT1
DVSS1 15 G2 Digital ground supply
DVCC1 16 H2 Digital power supply
P1.0/TA0CLK/ACLK 17 H1 I/O General-purpose digital I/O with port interrupt
TA0 clock signal TACLK input
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
P1.1/TA0.0 18 H4 I/O General-purpose digital I/O with port interrupt
TA0 CCR0 capture: CCI0A input, compare: Out0 output
BSL transmit output
P1.2/TA0.1 19 J4 I/O General-purpose digital I/O with port interrupt
TA0 CCR1 capture: CCI1A input, compare: Out1 output
BSL receive input
P1.3/TA0.2 20 J1 I/O General-purpose digital I/O with port interrupt
TA0 CCR2 capture: CCI2A input, compare: Out2 output
P1.4/TA0.3 21 J2 I/O General-purpose digital I/O with port interrupt
TA0 CCR3 capture: CCI3A input compare: Out3 output
P1.5/TA0.4 22 K1 I/O General-purpose digital I/O with port interrupt
TA0 CCR4 capture: CCI4A input, compare: Out4 output
P1.6/SMCLK 23 K2 I/O General-purpose digital I/O with port interrupt
SMCLK output
P1.7 24 L1 I/O General-purpose digital I/O with port interrupt
P2.0/TA1CLK/MCLK 25 M1 I/O General-purpose digital I/O with port interrupt
TA1 clock signal TA1CLK input
MCLK output
P2.1/TA1.0 26 L2 I/O General-purpose digital I/O with port interrupt
TA1 CCR0 capture: CCI0A input, compare: Out0 output
P2.2/TA1.1 27 M2 I/O General-purpose digital I/O with port interrupt
TA1 CCR1 capture: CCI1A input, compare: Out1 output
P2.3/TA1.2 28 L3 I/O General-purpose digital I/O with port interrupt
TA1 CCR2 capture: CCI2A input, compare: Out2 output
P2.4/RTCCLK 29 M3 I/O General-purpose digital I/O with port interrupt
RTCCLK output
P2.5 30 L4 I/O General-purpose digital I/O with port interrupt
P2.6/ACLK 31 M4 I/O General-purpose digital I/O with port interrupt
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
P2.7/ADC12CLK/DMAE0 32 J5 I/O General-purpose digital I/O with port interrupt
Conversion clock output ADC
DMA external trigger input
P3.0/UCB0STE/UCA0CLK 33 L5 I/O General-purpose digital I/O
Slave transmit enable – USCI_B0 SPI mode
Clock signal input – USCI_A0 SPI slave mode
Clock signal output – USCI_A0 SPI master mode
P3.1/UCB0SIMO/UCB0SDA 34 M5 I/O General-purpose digital I/O
Slave in, master out – USCI_B0 SPI mode
I2C data – USCI_B0 I2C mode
P3.2/UCB0SOMI/UCB0SCL 35 J6 I/O General-purpose digital I/O
Slave out, master in – USCI_B0 SPI mode
I2C clock – USCI_B0 I2C mode
P3.3/UCB0CLK/UCA0STE 36 L6 I/O General-purpose digital I/O
Clock signal input – USCI_B0 SPI slave mode
Clock signal output – USCI_B0 SPI master mode
Slave transmit enable – USCI_A0 SPI mode
DVSS3 37 M6 Digital ground supply
DVCC3 38 M7 Digital power supply
P3.4/UCA0TXD/UCA0SIMO 39 L7 I/O General-purpose digital I/O
Transmit data – USCI_A0 UART mode
Slave in, master out – USCI_A0 SPI mode
P3.5/UCA0RXD/UCA0SOMI 40 J7 I/O General-purpose digital I/O
Receive data – USCI_A0 UART mode
Slave out, master in – USCI_A0 SPI mode
P3.6/UCB1STE/UCA1CLK 41 M8 I/O General-purpose digital I/O
Slave transmit enable – USCI_B1 SPI mode
Clock signal input – USCI_A1 SPI slave mode
Clock signal output – USCI_A1 SPI master mode
P3.7/UCB1SIMO/UCB1SDA 42 L8 I/O General-purpose digital I/O
Slave in, master out – USCI_B1 SPI mode
I2C data – USCI_B1 I2C mode
P4.0/TB0.0 43 J8 I/O General-purpose digital I/O
TB0 capture CCR0: CCI0A/CCI0B input, compare: Out0 output
P4.1/TB0.1 44 M9 I/O General-purpose digital I/O
TB0 capture CCR1: CCI1A/CCI1B input, compare: Out1 output
P4.2/TB0.2 45 L9 I/O General-purpose digital I/O
TB0 capture CCR2: CCI2A/CCI2B input, compare: Out2 output
P4.3/TB0.3 46 L10 I/O General-purpose digital I/O
TB0 capture CCR3: CCI3A/CCI3B input, compare: Out3 output
P4.4/TB0.4 47 M10 I/O General-purpose digital I/O
TB0 capture CCR4: CCI4A/CCI4B input, compare: Out4 output
P4.5/TB0.5 48 L11 I/O General-purpose digital I/O
TB0 capture CCR5: CCI5A/CCI5B input, compare: Out5 output
P4.6/TB0.6 49 M11 I/O General-purpose digital I/O
TB0 capture CCR6: CCI6A/CCI6B input, compare: Out6 output
P4.7/TB0CLK/SMCLK 50 M12 I/O General-purpose digital I/O
TB0 clock input
SMCLK output
P5.4/UCB1SOMI/UCB1SCL 51 L12 I/O General-purpose digital I/O
Slave out, master in – USCI_B1 SPI mode
I2C clock – USCI_B1 I2C mode
P5.5/UCB1CLK/UCA1STE 52 J9 I/O General-purpose digital I/O
Clock signal input – USCI_B1 SPI slave mode
Clock signal output – USCI_B1 SPI master mode
Slave transmit enable – USCI_A1 SPI mode
P5.6/UCA1TXD/UCA1SIMO 53 K11 I/O General-purpose digital I/O
Transmit data – USCI_A1 UART mode
Slave in, master out – USCI_A1 SPI mode
P5.7/UCA1RXD/UCA1SOMI 54 K12 I/O General-purpose digital I/O
Receive data – USCI_A1 UART mode
Slave out, master in – USCI_A1 SPI mode
P7.2/TB0OUTH/SVMOUT 55 J11 I/O General-purpose digital I/O
Switch all PWM outputs high impedance – Timer TB0
SVM output
P7.3/TA1.2 56 J12 I/O General-purpose digital I/O
TA1 CCR2 capture: CCI2B input, compare: Out2 output
P8.0/TA0.0 57 H9 I/O General-purpose digital I/O
TA0 CCR0 capture: CCI0B input, compare: Out0 output
P8.1/TA0.1 58 H11 I/O General-purpose digital I/O
TA0 CCR1 capture: CCI1B input, compare: Out1 output
P8.2/TA0.2 59 H12 I/O General-purpose digital I/O
TA0 CCR2 capture: CCI2B input, compare: Out2 output
P8.3/TA0.3 60 G9 I/O General-purpose digital I/O
TA0 CCR3 capture: CCI3B input, compare: Out3 output
P8.4/TA0.4 61 G11 I/O General-purpose digital I/O
TA0 CCR4 capture: CCI4B input, compare: Out4 output
VCORE(2) 62 G12 Regulated core power supply output (internal use only, no external current loading)
DVSS2 63 F12 Digital ground supply
DVCC2 64 E12 Digital power supply
P8.5/TA1.0 65 F11 I/O General-purpose digital I/O
TA1 CCR0 capture: CCI0B input, compare: Out0 output
P8.6/TA1.1 66 E11 I/O General-purpose digital I/O
TA1 CCR1 capture: CCI1B input, compare: Out1 output
P8.7 67 D12 I/O General-purpose digital I/O
P9.0/UCB2STE/UCA2CLK 68 D11 I/O General-purpose digital I/O
Slave transmit enable – USCI_B2 SPI mode
Clock signal input – USCI_A2 SPI slave mode
Clock signal output – USCI_A2 SPI master mode
P9.1/UCB2SIMO/UCB2SDA 69 F9 I/O General-purpose digital I/O
Slave in, master out – USCI_B2 SPI mode
I2C data – USCI_B2 I2C mode
P9.2/UCB2SOMI/UCB2SCL 70 C12 I/O General-purpose digital I/O
Slave out, master in – USCI_B2 SPI mode
I2C clock – USCI_B2 I2C mode
P9.3/UCB2CLK/UCA2STE 71 E9 I/O General-purpose digital I/O
Clock signal input – USCI_B2 SPI slave mode
Clock signal output – USCI_B2 SPI master mode
Slave transmit enable – USCI_A2 SPI mode
P9.4/UCA2TXD/UCA2SIMO 72 C11 I/O General-purpose digital I/O
Transmit data – USCI_A2 UART mode
Slave in, master out – USCI_A2 SPI mode
P9.5/UCA2RXD/UCA2SOMI 73 B12 I/O General-purpose digital I/O
Receive data – USCI_A2 UART mode
Slave out, master in – USCI_A2 SPI mode
P9.6 74 B11 I/O General-purpose digital I/O
P9.7 75 A12 I/O General-purpose digital I/O
P10.0/UCB3STE/UCA3CLK 76 D9 I/O General-purpose digital I/O
Slave transmit enable – USCI_B3 SPI mode
Clock signal input – USCI_A3 SPI slave mode
Clock signal output – USCI_A3 SPI master mode
P10.1/UCB3SIMO/UCB3SDA 77 A11 I/O General-purpose digital I/O
Slave in, master out – USCI_B3 SPI mode
I2C data – USCI_B3 I2C mode
P10.2/UCB3SOMI/UCB3SCL 78 D8 I/O General-purpose digital I/O
Slave out, master in – USCI_B3 SPI mode
I2C clock – USCI_B3 I2C mode
P10.3/UCB3CLK/UCA3STE 79 B10 I/O General-purpose digital I/O
Clock signal input – USCI_B3 SPI slave mode
Clock signal output – USCI_B3 SPI master mode
Slave transmit enable – USCI_A3 SPI mode
P10.4/UCA3TXD/UCA3SIMO 80 A10 I/O General-purpose digital I/O
Transmit data – USCI_A3 UART mode
Slave in, master out – USCI_A3 SPI mode
P10.5/UCA3RXD/UCA3SOMI 81 B9 I/O General-purpose digital I/O
Receive data – USCI_A3 UART mode
Slave out, master in – USCI_A3 SPI mode
P10.6 82 A9 I/O General-purpose digital I/O
P10.7 83 B8 I/O General-purpose digital I/O
P11.0/ACLK 84 A8 I/O General-purpose digital I/O
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
P11.1/MCLK 85 D7 I/O General-purpose digital I/O
MCLK output
P11.2/SMCLK 86 A7 I/O General-purpose digital I/O
SMCLK output
DVCC4 87 B7 Digital power supply
DVSS4 88 B6 Digital ground supply
P5.2/XT2IN 89 A6 I/O General-purpose digital I/O
Input terminal for crystal oscillator XT2
P5.3/XT2OUT 90 A5 I/O General-purpose digital I/O
Output terminal of crystal oscillator XT2
TEST/SBWTCK(3) 91 D6 I Test mode pin – Selects four wire JTAG operation.
Spy-Bi-Wire input clock when Spy-Bi-Wire operation activated
PJ.0/TDO(4) 92 B5 I/O General-purpose digital I/O
JTAG test data output port
PJ.1/TDI/TCLK(4) 93 A4 I/O General-purpose digital I/O
JTAG test data input or test clock input
PJ.2/TMS(4) 94 D5 I/O General-purpose digital I/O
JTAG test mode select
PJ.3/TCK(4) 95 B4 I/O General-purpose digital I/O
JTAG test clock
RST/NMI/SBWTDIO(3) 96 A3 I/O Reset input active low(5)
Nonmaskable interrupt input
Spy-Bi-Wire data input/output when Spy-Bi-Wire operation activated.
P6.0/A0 97 D4 I/O General-purpose digital I/O
Analog input A0 – ADC
P6.1/A1 98 B3 I/O General-purpose digital I/O
Analog input A1 – ADC
P6.2/A2 99 A2 I/O General-purpose digital I/O
Analog input A2 – ADC
P6.3/A3 100 B2 I/O General-purpose digital I/O
Analog input A3 – ADC
Reserved N/A G5, E8, F8, G8, H8, E7, H7, E6, H6, E5, F5, H5, C3 Reserved. Connect to ground.
(1) I = input, O = output, N/A = not available on this package offering
(2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended capacitor value, CVCORE.
(3) See Section 6.5 and Section 6.6 for use with BSL and JTAG functions, respectively.
(4) See Section 6.6 for use with JTAG function.
(5) When this pin is configured as reset, the internal pullup resistor is enabled by default.