SLAS541L June   2007  – May 2020 MSP430F2416 , MSP430F2417 , MSP430F2418 , MSP430F2419 , MSP430F2616 , MSP430F2617 , MSP430F2618 , MSP430F2619

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagrams
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Typical Characteristics – Active Mode Supply Current (Into VCC)
    6. 5.6  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    7. 5.7  Typical Characteristics – LPM4 Current
    8. 5.8  Schmitt-Trigger Inputs (Ports P1 to P8, RST/NMI, JTAG, XIN, and XT2IN)
    9. 5.9  Inputs (Ports P1 and P2)
    10. 5.10 Leakage Current (Ports P1 to P8)
    11. 5.11 Standard Inputs (RST/NMI)
    12. 5.12 Outputs (Ports P1 to P8)
    13. 5.13 Output Frequency (Ports P1 to P8)
    14. 5.14 Typical Characteristics – Outputs
    15. 5.15 POR and Brownout Reset (BOR)
    16. 5.16 Typical Characteristics – POR and BOR
    17. 5.17 Supply Voltage Supervisor (SVS), Supply Voltage Monitor (SVM)
    18. 5.18 Main DCO Characteristics
    19. 5.19 DCO Frequency
    20. 5.20 Calibrated DCO Frequencies – Tolerance at Calibration
    21. 5.21 Calibrated DCO Frequencies – Tolerance Over Temperature 0°C to 85°C
    22. 5.22 Calibrated DCO Frequencies – Tolerance Over Supply Voltage VCC
    23. 5.23 Calibrated DCO Frequencies – Overall Tolerance
    24. 5.24 Typical Characteristics – Calibrated DCO Frequency
    25. 5.25 Wake-up Times From Lower-Power Modes (LPM3, LPM4)
    26. 5.26 Typical Characteristics – DCO Clock Wake-up Time From LPM3 or LPM4
    27. 5.27 DCO With External Resistor ROSC
    28. 5.28 Typical Characteristics – DCO With External Resistor ROSC
    29. 5.29 Crystal Oscillator LFXT1, Low-Frequency Mode
    30. 5.30 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    31. 5.31 Crystal Oscillator LFXT1, High-Frequency Mode
    32. 5.32 Typical Characteristics – LFXT1 Oscillator in HF Mode (XTS = 1)
    33. 5.33 Crystal Oscillator XT2
    34. 5.34 Typical Characteristics – XT2 Oscillator
    35. 5.35 Timer_A
    36. 5.36 Timer_B
    37. 5.37 USCI (UART Mode)
    38. 5.38 USCI (SPI Master Mode)
    39. 5.39 USCI (SPI Slave Mode)
    40. 5.40 USCI (I2C Mode)
    41. 5.41 Comparator_A+
    42. 5.42 Typical Characteristics, Comparator_A+
    43. 5.43 12-Bit ADC Power Supply and Input Range Conditions
    44. 5.44 12-Bit ADC External Reference
    45. 5.45 12-Bit ADC Built-In Reference
    46. 5.46 12-Bit ADC Timing Parameters
    47. 5.47 12-Bit ADC Linearity Parameters
    48. 5.48 12-Bit ADC Temperature Sensor and Built-In VMID
    49. 5.49 12-Bit DAC Supply Specifications
    50. 5.50 12-Bit DAC Linearity Specifications
    51. 5.51 Typical Characteristics, 12-Bit DAC Linearity Specifications
    52. 5.52 12-Bit DAC Output Specifications
    53. 5.53 12-Bit DAC Reference Input Specifications
    54. 5.54 12-Bit DAC Dynamic Specifications
    55. 5.55 Flash Memory
    56. 5.56 RAM
    57. 5.57 JTAG Interface
    58. 5.58 JTAG Fuse
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Instruction Set
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Special Function Registers (SFRs)
      1. Table 6-4 Interrupt Enable Register 1 Description
      2. Table 6-5 Interrupt Enable Register 2 Description
      3. Table 6-6 Interrupt Flag Register 1 Description
      4. Table 6-7 Interrupt Flag Register 2 Description
    6. 6.6  Memory Organization
    7. 6.7  Bootloader (BSL)
    8. 6.8  Flash Memory
    9. 6.9  Peripherals
      1. 6.9.1  DMA Controller (MSP430F261x Only)
      2. 6.9.2  Oscillator and System Clock
      3. 6.9.3  Calibration Data Stored in Information Memory Segment A
      4. 6.9.4  Brownout, Supply Voltage Supervisor (SVS)
      5. 6.9.5  Digital I/O
      6. 6.9.6  Watchdog Timer (WDT+)
      7. 6.9.7  Hardware Multiplier
      8. 6.9.8  Universal Serial Communication Interface (USCI)
      9. 6.9.9  Timer_A3
      10. 6.9.10 Timer_B7
      11. 6.9.11 Comparator_A+
      12. 6.9.12 ADC12
      13. 6.9.13 DAC12 (MSP430F261x Only)
      14. 6.9.14 Peripheral File Map
    10. 6.10 Port Diagrams
      1. 6.10.1  Port P1 (P1.0 to P1.7), Input/Output With Schmitt Trigger
      2. 6.10.2  Port P2 (P2.0 to P2.4, P2.6, and P2.7), Input/Output With Schmitt Trigger
      3. 6.10.3  Port P2 (P2.5), Input/Output With Schmitt Trigger
      4. 6.10.4  Port P3 (P3.0 to P3.7), Input/Output With Schmitt Trigger
      5. 6.10.5  Port P4 (P4.0 to P4.7), Input/Output With Schmitt Trigger
      6. 6.10.6  Port P5 (P5.0 to P5.7), Input/Output With Schmitt Trigger
      7. 6.10.7  Port P6 (P6.0 to P6.4), Input/Output With Schmitt Trigger
      8. 6.10.8  Port P6 (P6.5 and P6.6), Input/Output With Schmitt Trigger
      9. 6.10.9  Port P6 (P6.7), Input/Output With Schmitt Trigger
      10. 6.10.10 Port P7 (P7.0 to P7.7), Input/Output With Schmitt Trigger
      11. 6.10.11 Port P8 (P8.0 to P8.5), Input/Output With Schmitt Trigger
      12. 6.10.12 Port P8 (P8.6), Input/Output With Schmitt Trigger
      13. 6.10.13 Port P8 (P8.7), Input/Output With Schmitt Trigger
      14. 6.10.14 JTAG Pins (TMS, TCK, TDI/TCLK, TDO/TDI) Input/Output With Schmitt Trigger
      15. 6.10.15 JTAG Fuse Check Mode
  7. 7Device and Documentation Support
    1. 7.1  Getting Started
    2. 7.2  Device Nomenclature
    3. 7.3  Tools and Software
    4. 7.4  Documentation Support
    5. 7.5  Related Links
    6. 7.6  Community Resources
    7. 7.7  Trademarks
    8. 7.8  Electrostatic Discharge Caution
    9. 7.9  Export Control Notice
    10. 7.10 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Special Function Registers (SFRs)

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement.

Legend
rw Bit can be read and written.
rw-0, rw-1 Bit can be read and written. It is Reset or Set by PUC.
rw-(0), rw-(1) Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device.
Figure 6-2 Interrupt Enable Register 1 (Address = 00h)
7 6 5 4 3 2 1 0
ACCVIE NMIIE OFIE WDTIE
rw-0 rw-0 rw-0 rw-0

Table 6-4 Interrupt Enable Register 1 Description

BIT FIELD TYPE RESET DESCRIPTION
5 ACCVIE RW 0h Flash access violation interrupt enable
4 NMIIE RW 0h (Non)maskable interrupt enable
1 OFIE RW 0h Oscillator fault interrupt enable
0 WDTIE RW 0h Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if the watchdog timer is configured in interval timer mode.
Figure 6-3 Interrupt Enable Register 2 (Address = 01h)
7 6 5 4 3 2 1 0
  UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE
  rw-0 rw-0 rw-0 rw-0

Table 6-5 Interrupt Enable Register 2 Description

BIT FIELD TYPE RESET DESCRIPTION
3 UCB0TXIE RW 0h USCI_B0 transmit interrupt enable
2 UCB0RXIE RW 0h USCI_B0 receive interrupt enable
1 UCA0TXIE RW 0h USCI_A0 transmit interrupt enable
0 UCA0RXIE RW 0h USCI_A0 receive interrupt enable
Figure 6-4 Interrupt Flag Register 1 (Address = 02h)
7 6 5 4 3 2 1 0
NMIIFG RSTIFG PORIFG OFIFG WDTIFG
rw-0 rw-(0) rw-(1) rw-1 rw-(0)

Table 6-6 Interrupt Flag Register 1 Description

BIT FIELD TYPE RESET DESCRIPTION
4 NMIIFG RW 0h Set by the RST/NMI pin
3 RSTIFG RW 0h External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power up.
2 PORIFG RW 1h Power-on reset interrupt flag. Set on VCC power up.
1 OFIFG RW 1h Flag set on oscillator fault.
0 WDTIFG RW 0h Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power on or a reset condition at the RST/NMI pin in reset mode.
Figure 6-5 Interrupt Flag Register 2 (Address = 03h)
7 6 5 4 3 2 1 0
  UCB0TXIFG UCB0RXIFG UCA0TXIFG UCA0RXIFG
  rw-1 rw-0 rw-1 rw-0

Table 6-7 Interrupt Flag Register 2 Description

BIT FIELD TYPE RESET DESCRIPTION
3 UCB0TXIFG RW 0h USCI_B0 transmit interrupt flag
2 UCB0RXIFG RW 1h USCI_B0 receive interrupt flag
1 UCA0TXIFG RW 1h USCI_A0 transmit interrupt flag
0 UCA0RXIFG RW 0h USCI_A0 receive interrupt flag