SLAS655G January   2010  – September 2020 MSP430F5418A , MSP430F5419A , MSP430F5435A , MSP430F5436A , MSP430F5437A , MSP430F5438A

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Functional Block Diagrams
  5. Revision History
  6. Device Comparison
    1. 6.1 Related Products
  7. Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Signal Descriptions
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 8.6  Thermal Resistance Characteristics
    7. 8.7  Schmitt-Trigger Inputs – General-Purpose I/O
    8. 8.8  Inputs – Ports P1 and P2
    9. 8.9  Leakage Current – General-Purpose I/O
    10. 8.10 Outputs – General-Purpose I/O (Full Drive Strength)
    11. 8.11 Outputs – General-Purpose I/O (Reduced Drive Strength)
    12. 8.12 Output Frequency – General-Purpose I/O
    13. 8.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 8.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    15. 8.15 Crystal Oscillator, XT1, Low-Frequency Mode
    16. 8.16 Crystal Oscillator, XT1, High-Frequency Mode
    17. 8.17 Crystal Oscillator, XT2
    18. 8.18 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    19. 8.19 Internal Reference, Low-Frequency Oscillator (REFO)
    20. 8.20 DCO Frequency
    21. 8.21 PMM, Brownout Reset (BOR)
    22. 8.22 PMM, Core Voltage
    23. 8.23 PMM, SVS High Side
    24. 8.24 PMM, SVM High Side
    25. 8.25 PMM, SVS Low Side
    26. 8.26 PMM, SVM Low Side
    27. 8.27 Wake-up Times From Low-Power Modes and Reset
    28. 8.28 Timer_A
    29. 8.29 Timer_B
    30. 8.30 USCI (UART Mode) Clock Frequency
    31. 8.31 USCI (UART Mode)
    32. 8.32 USCI (SPI Master Mode) Clock Frequency
    33. 8.33 USCI (SPI Master Mode)
    34. 8.34 USCI (SPI Slave Mode)
    35. 8.35 USCI (I2C Mode)
    36. 8.36 12-Bit ADC, Power Supply and Input Range Conditions
    37. 8.37 12-Bit ADC, Timing Parameters
    38. 8.38 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage
    39. 8.39 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
    40. 8.40 12-Bit ADC, Temperature Sensor and Built-In VMID
    41. 8.41 REF, External Reference
    42. 8.42 REF, Built-In Reference
    43. 8.43 Flash Memory
    44. 8.44 JTAG and Spy-Bi-Wire Interface
  9. Detailed Description
    1. 9.1  CPU
    2. 9.2  Operating Modes
    3. 9.3  Interrupt Vector Addresses
    4. 9.4  Memory Organization
    5. 9.5  Bootloader (BSL)
    6. 9.6  JTAG Operation
      1. 9.6.1 JTAG Standard Interface
      2. 9.6.2 Spy-Bi-Wire Interface
    7. 9.7  Flash Memory
    8. 9.8  RAM
    9. 9.9  Peripherals
      1. 9.9.1  Digital I/O
      2. 9.9.2  Oscillator and System Clock
      3. 9.9.3  Power-Management Module (PMM)
      4. 9.9.4  Hardware Multiplier (MPY)
      5. 9.9.5  Real-Time Clock (RTC_A)
      6. 9.9.6  Watchdog Timer (WDT_A)
      7. 9.9.7  System Module (SYS)
      8. 9.9.8  DMA Controller
      9. 9.9.9  Universal Serial Communication Interface (USCI)
      10. 9.9.10 TA0
      11. 9.9.11 TA1
      12. 9.9.12 TB0
      13. 9.9.13 ADC12_A
      14. 9.9.14 CRC16
      15. 9.9.15 Reference (REF) Module Voltage Reference
      16. 9.9.16 Embedded Emulation Module (EEM) (L Version)
      17. 9.9.17 Peripheral File Map
    10. 9.10 Input/Output Diagrams
      1. 9.10.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 9.10.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 9.10.3  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 9.10.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 9.10.5  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      6. 9.10.6  Port P5 (P5.2 and P5.3) Input/Output With Schmitt Trigger
      7. 9.10.7  Port P5 (P5.4 to P5.7) Input/Output With Schmitt Trigger
      8. 9.10.8  Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      9. 9.10.9  Port P7 (P7.0 and P7.1) Input/Output With Schmitt Trigger
      10. 9.10.10 Port P7 (P7.2 and P7.3) Input/Output With Schmitt Trigger
      11. 9.10.11 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
      12. 9.10.12 Port P8 (P8.0 to P8.7) Input/Output With Schmitt Trigger
      13. 9.10.13 Port P9 (P9.0 to P9.7) Input/Output With Schmitt Trigger
      14. 9.10.14 Port P10 (P10.0 to P10.7) Input/Output With Schmitt Trigger
      15. 9.10.15 Port P11 (P11.0 to P11.2) Input/Output With Schmitt Trigger
      16. 9.10.16 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      17. 9.10.17 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    11. 9.11 Device Descriptors
  10. 10Device and Documentation Support
    1. 10.1  Getting Started
    2. 10.2  Device Nomenclature
    3. 10.3  Tools and Software
    4. 10.4  Documentation Support
    5. 10.5  Related Links
    6. 10.6  Support Resources
    7. 10.7  Trademarks
    8. 10.8  Electrostatic Discharge Caution
    9. 10.9  Export Control Notice
    10. 10.10 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Signal Descriptions

Section 7.2 describes the signals for all device variants and package options.

Table 7-1 Signal Descriptions
TERMINAL I/O(1) DESCRIPTION
NAME NO.
PZ PN ZCA, ZQW
P6.4/A4 1 1 A1 I/O General-purpose digital I/O
Analog input A4 for the ADC
P6.5/A5 2 2 E4 I/O General-purpose digital I/O
Analog input A5 for the ADC
P6.6/A6 3 3 B1 I/O General-purpose digital I/O
Analog input A6 for the ADC
P6.7/A7 4 4 C2 I/O General-purpose digital I/O
Analog input A7 for the ADC
P7.4/A12 5 5 F4 I/O General-purpose digital I/O
Analog input A12 for the ADC
P7.5/A13 6 6 C1 I/O General-purpose digital I/O
Analog input A13 for the ADC
P7.6/A14 7 7 D2 I/O General-purpose digital I/O
Analog input A14 for the ADC
P7.7/A15 8 8 G4 I/O General-purpose digital I/O
Analog input A15 for the ADC
P5.0/A8/VREF+/VeREF+ 9 9 D1 I/O General-purpose digital I/O
Analog input A8 for the ADC
Output of reference voltage to the ADC
Input for an external reference voltage to the ADC
P5.1/A9/VREF-/VeREF- 10 10 E1 I/O General-purpose digital I/O
Analog input A9 for the ADC
Negative terminal for the ADC reference voltage for both sources, the internal reference voltage, or an external applied reference voltage
AVCC 11 11 E2 Analog power supply
AVSS 12 12 F2 Analog ground supply
P7.0/XIN 13 13 F1 I/O General-purpose digital I/O
Input terminal for crystal oscillator XT1
P7.1/XOUT 14 14 G1 I/O General-purpose digital I/O
Output terminal of crystal oscillator XT1
DVSS1 15 15 G2 Digital ground supply
DVCC1 16 16 H2 Digital power supply
P1.0/TA0CLK/ACLK 17 17 H1 I/O General-purpose digital I/O with port interrupt
TA0 clock signal TACLK input
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
P1.1/TA0.0 18 18 H4 I/O General-purpose digital I/O with port interrupt
TA0 CCR0 capture: CCI0A input, compare: Out0 output
BSL transmit output
P1.2/TA0.1 19 19 J4 I/O General-purpose digital I/O with port interrupt
TA0 CCR1 capture: CCI1A input, compare: Out1 output
BSL receive input
P1.3/TA0.2 20 20 J1 I/O General-purpose digital I/O with port interrupt
TA0 CCR2 capture: CCI2A input, compare: Out2 output
P1.4/TA0.3 21 21 J2 I/O General-purpose digital I/O with port interrupt
TA0 CCR3 capture: CCI3A input compare: Out3 output
P1.5/TA0.4 22 22 K1 I/O General-purpose digital I/O with port interrupt
TA0 CCR4 capture: CCI4A input, compare: Out4 output
P1.6/SMCLK 23 23 K2 I/O General-purpose digital I/O with port interrupt
SMCLK output
P1.7 24 24 L1 I/O General-purpose digital I/O with port interrupt
P2.0/TA1CLK/MCLK 25 25 M1 I/O General-purpose digital I/O with port interrupt
TA1 clock signal TA1CLK input
MCLK output
P2.1/TA1.0 26 26 L2 I/O General-purpose digital I/O with port interrupt
TA1 CCR0 capture: CCI0A input, compare: Out0 output
P2.2/TA1.1 27 27 M2 I/O General-purpose digital I/O with port interrupt
TA1 CCR1 capture: CCI1A input, compare: Out1 output
P2.3/TA1.2 28 28 L3 I/O General-purpose digital I/O with port interrupt
TA1 CCR2 capture: CCI2A input, compare: Out2 output
P2.4/RTCCLK 29 29 M3 I/O General-purpose digital I/O with port interrupt
RTCCLK output
P2.5 30 32 L4 I/O General-purpose digital I/O with port interrupt
P2.6/ACLK 31 33 M4 I/O General-purpose digital I/O with port interrupt
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
P2.7/ADC12CLK/DMAE0 32 34 J5 I/O General-purpose digital I/O with port interrupt
Conversion clock output for the ADC
DMA external trigger input
P3.0/UCB0STE/UCA0CLK 33 35 L5 I/O General-purpose digital I/O
Slave transmit enable – USCI_B0 SPI mode
Clock signal input – USCI_A0 SPI slave mode
Clock signal output – USCI_A0 SPI master mode
P3.1/UCB0SIMO/UCB0SDA 34 36 M5 I/O General-purpose digital I/O
Slave in, master out – USCI_B0 SPI mode
I2C data – USCI_B0 I2C mode
P3.2/UCB0SOMI/UCB0SCL 35 37 J6 I/O General-purpose digital I/O
Slave out, master in – USCI_B0 SPI mode
I2C clock – USCI_B0 I2C mode
P3.3/UCB0CLK/UCA0STE 36 38 L6 I/O General-purpose digital I/O
Clock signal input – USCI_B0 SPI slave mode
Clock signal output – USCI_B0 SPI master mode
Slave transmit enable – USCI_A0 SPI mode
DVSS3 37 30 M6 Digital ground supply
DVCC3 38 31 M7 Digital power supply
P3.4/UCA0TXD/UCA0SIMO 39 39 L7 I/O General-purpose digital I/O
Transmit data – USCI_A0 UART mode
Slave in, master out – USCI_A0 SPI mode
P3.5/UCA0RXD/UCA0SOMI 40 40 J7 I/O General-purpose digital I/O
Receive data – USCI_A0 UART mode
Slave out, master in – USCI_A0 SPI mode
P3.6/UCB1STE/UCA1CLK 41 41 M8 I/O General-purpose digital I/O
Slave transmit enable – USCI_B1 SPI mode
Clock signal input – USCI_A1 SPI slave mode
Clock signal output – USCI_A1 SPI master mode
P3.7/UCB1SIMO/UCB1SDA 42 42 L8 I/O General-purpose digital I/O
Slave in, master out – USCI_B1 SPI mode
I2C data – USCI_B1 I2C mode
P4.0/TB0.0 43 43 J8 I/O General-purpose digital I/O
TB0 capture CCR0: CCI0A/CCI0B input, compare: Out0 output
P4.1/TB0.1 44 44 M9 I/O General-purpose digital I/O
TB0 capture CCR1: CCI1A/CCI1B input, compare: Out1 output
P4.2/TB0.2 45 45 L9 I/O General-purpose digital I/O
TB0 capture CCR2: CCI2A/CCI2B input, compare: Out2 output
P4.3/TB0.3 46 46 L10 I/O General-purpose digital I/O
TB0 capture CCR3: CCI3A/CCI3B input, compare: Out3 output
P4.4/TB0.4 47 47 M10 I/O General-purpose digital I/O
TB0 capture CCR4: CCI4A/CCI4B input, compare: Out4 output
P4.5/TB0.5 48 48 L11 I/O General-purpose digital I/O
TB0 capture CCR5: CCI5A/CCI5B input, compare: Out5 output
P4.6/TB0.6 49 52 M11 I/O General-purpose digital I/O
TB0 capture CCR6: CCI6A/CCI6B input, compare: Out6 output
P4.7/TB0CLK/SMCLK 50 53 M12 I/O General-purpose digital I/O
TB0 clock input
SMCLK output
P5.4/UCB1SOMI/UCB1SCL 51 54 L12 I/O General-purpose digital I/O
Slave out, master in – USCI_B1 SPI mode
I2C clock – USCI_B1 I2C mode
P5.5/UCB1CLK/UCA1STE 52 55 J9 I/O General-purpose digital I/O
Clock signal input – USCI_B1 SPI slave mode
Clock signal output – USCI_B1 SPI master mode
Slave transmit enable – USCI_A1 SPI mode
P5.6/UCA1TXD/UCA1SIMO 53 56 K11 I/O General-purpose digital I/O
Transmit data – USCI_A1 UART mode
Slave in, master out – USCI_A1 SPI mode
P5.7/UCA1RXD/UCA1SOMI 54 57 K12 I/O General-purpose digital I/O
Receive data – USCI_A1 UART mode
Slave out, master in – USCI_A1 SPI mode
P7.2/TB0OUTH/SVMOUT 55 58 J11 I/O General-purpose digital I/O
Switch all PWM outputs to high impedance – Timer TB0
SVM output
P7.3/TA1.2 56 59 J12 I/O General-purpose digital I/O
TA1 CCR2 capture: CCI2B input, compare: Out2 output
P8.0/TA0.0 57 60 H9 I/O General-purpose digital I/O
TA0 CCR0 capture: CCI0B input, compare: Out0 output
P8.1/TA0.1 58 61 H11 I/O General-purpose digital I/O
TA0 CCR1 capture: CCI1B input, compare: Out1 output
P8.2/TA0.2 59 62 H12 I/O General-purpose digital I/O
TA0 CCR2 capture: CCI2B input, compare: Out2 output
P8.3/TA0.3 60 63 G9 I/O General-purpose digital I/O
TA0 CCR3 capture: CCI3B input, compare: Out3 output
P8.4/TA0.4 61 64 G11 I/O General-purpose digital I/O
TA0 CCR4 capture: CCI4B input, compare: Out4 output
VCORE(3) 62 49 G12 Regulated core power supply output (internal use only, no external current loading)
DVSS2 63 50 F12 Digital ground supply
DVCC2 64 51 E12 Digital power supply
P8.5/TA1.0 65 65 F11 I/O General-purpose digital I/O
TA1 CCR0 capture: CCI0B input, compare: Out0 output
P8.6/TA1.1 66 66 E11 I/O General-purpose digital I/O
TA1 CCR1 capture: CCI1B input, compare: Out1 output
P8.7 67 N/A D12 I/O General-purpose digital I/O
P9.0/UCB2STE/UCA2CLK 68 N/A D11 I/O General-purpose digital I/O
Slave transmit enable – USCI_B2 SPI mode
Clock signal input – USCI_A2 SPI slave mode
Clock signal output – USCI_A2 SPI master mode
P9.1/UCB2SIMO/UCB2SDA 69 N/A F9 I/O General-purpose digital I/O
Slave in, master out – USCI_B2 SPI mode
I2C data – USCI_B2 I2C mode
P9.2/UCB2SOMI/UCB2SCL 70 N/A C12 I/O General-purpose digital I/O
Slave out, master in – USCI_B2 SPI mode
I2C clock – USCI_B2 I2C mode
P9.3/UCB2CLK/UCA2STE 71 N/A E9 I/O General-purpose digital I/O
Clock signal input – USCI_B2 SPI slave mode
Clock signal output – USCI_B2 SPI master mode
Slave transmit enable – USCI_A2 SPI mode
P9.4/UCA2TXD/UCA2SIMO 72 N/A C11 I/O General-purpose digital I/O
Transmit data – USCI_A2 UART mode
Slave in, master out – USCI_A2 SPI mode
P9.5/UCA2RXD/UCA2SOMI 73 N/A B12 I/O General-purpose digital I/O
Receive data – USCI_A2 UART mode
Slave out, master in – USCI_A2 SPI mode
P9.6 74 N/A B11 I/O General-purpose digital I/O
P9.7 75 N/A A12 I/O General-purpose digital I/O
P10.0/UCB3STE/UCA3CLK 76 N/A D9 I/O General-purpose digital I/O
Slave transmit enable – USCI_B3 SPI mode
Clock signal input – USCI_A3 SPI slave mode
Clock signal output – USCI_A3 SPI master mode
P10.1/UCB3SIMO/UCB3SDA 77 N/A A11 I/O General-purpose digital I/O
Slave in, master out – USCI_B3 SPI mode
I2C data – USCI_B3 I2C mode
P10.2/UCB3SOMI/UCB3SCL 78 N/A D8 I/O General-purpose digital I/O
Slave out, master in – USCI_B3 SPI mode
I2C clock – USCI_B3 I2C mode
P10.3/UCB3CLK/UCA3STE 79 N/A B10 I/O General-purpose digital I/O
Clock signal input – USCI_B3 SPI slave mode
Clock signal output – USCI_B3 SPI master mode
Slave transmit enable – USCI_A3 SPI mode
P10.4/UCA3TXD/UCA3SIMO 80 N/A A10 I/O General-purpose digital I/O
Transmit data – USCI_A3 UART mode
Slave in, master out – USCI_A3 SPI mode
P10.5/UCA3RXD/UCA3SOMI 81 N/A B9 I/O General-purpose digital I/O
Receive data – USCI_A3 UART mode
Slave out, master in – USCI_A3 SPI mode
P10.6 82 N/A A9 I/O General-purpose digital I/O
P10.7 83 N/A B8 I/O General-purpose digital I/O
P11.0/ACLK 84 N/A A8 I/O General-purpose digital I/O
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
P11.1/MCLK 85 N/A D7 I/O General-purpose digital I/O
MCLK output
P11.2/SMCLK 86 N/A A7 I/O General-purpose digital I/O
SMCLK output
DVCC4 87 67 B7 Digital power supply
DVSS4 88 68 B6 Digital ground supply
P5.2/XT2IN 89 69 A6 I/O General-purpose digital I/O
Input terminal for crystal oscillator XT2
P5.3/XT2OUT 90 70 A5 I/O General-purpose digital I/O
Output terminal of crystal oscillator XT2
TEST/SBWTCK(4) 91 71 D6 I Test mode pin – Selects four wire JTAG operation.
Spy-Bi-Wire input clock when Spy-Bi-Wire operation activated
PJ.0/TDO(5) 92 72 B5 I/O General-purpose digital I/O
JTAG test data output port
PJ.1/TDI/TCLK(5) 93 73 A4 I/O General-purpose digital I/O
JTAG test data input or test clock input
PJ.2/TMS(5) 94 74 D5 I/O General-purpose digital I/O
JTAG test mode select
PJ.3/TCK(5) 95 75 B4 I/O General-purpose digital I/O
JTAG test clock
RST/NMI/SBWTDIO(4) 96 76 A3 I/O Reset input active low(6)
Nonmaskable interrupt input
Spy-Bi-Wire data input/output when Spy-Bi-Wire operation activated.
P6.0/A0 97 77 D4 I/O General-purpose digital I/O
Analog input A0 for the ADC
P6.1/A1 98 78 B3 I/O General-purpose digital I/O
Analog input A1 for the ADC
P6.2/A2 99 79 A2 I/O General-purpose digital I/O
Analog input A2 for the ADC
P6.3/A3 100 80 B2 I/O General-purpose digital I/O
Analog input A3 for the ADC
Reserved N/A N/A  (2)
I = input, O = output, N/A = not available on this package offering
C3, E5, E6, E7, E8, F5, F8, G5, G8, H5, H6, H7, H8 are reserved and should be connected to ground.
VCORE is for internal use only. No external current loading is possible. VCORE should be connected to only the recommended capacitor value, CVCORE.
See Section 9.5 and Section 9.6 for use with BSL and JTAG functions, respectively.
See Section 9.6 for use with JTAG function.
When this pin is configured as reset, the internal pullup resistor is enabled by default.