SLAS655G January   2010  – September 2020 MSP430F5418A , MSP430F5419A , MSP430F5435A , MSP430F5436A , MSP430F5437A , MSP430F5438A

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Functional Block Diagrams
  5. Revision History
  6. Device Comparison
    1. 6.1 Related Products
  7. Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Signal Descriptions
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 8.6  Thermal Resistance Characteristics
    7. 8.7  Schmitt-Trigger Inputs – General-Purpose I/O
    8. 8.8  Inputs – Ports P1 and P2
    9. 8.9  Leakage Current – General-Purpose I/O
    10. 8.10 Outputs – General-Purpose I/O (Full Drive Strength)
    11. 8.11 Outputs – General-Purpose I/O (Reduced Drive Strength)
    12. 8.12 Output Frequency – General-Purpose I/O
    13. 8.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 8.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    15. 8.15 Crystal Oscillator, XT1, Low-Frequency Mode
    16. 8.16 Crystal Oscillator, XT1, High-Frequency Mode
    17. 8.17 Crystal Oscillator, XT2
    18. 8.18 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    19. 8.19 Internal Reference, Low-Frequency Oscillator (REFO)
    20. 8.20 DCO Frequency
    21. 8.21 PMM, Brownout Reset (BOR)
    22. 8.22 PMM, Core Voltage
    23. 8.23 PMM, SVS High Side
    24. 8.24 PMM, SVM High Side
    25. 8.25 PMM, SVS Low Side
    26. 8.26 PMM, SVM Low Side
    27. 8.27 Wake-up Times From Low-Power Modes and Reset
    28. 8.28 Timer_A
    29. 8.29 Timer_B
    30. 8.30 USCI (UART Mode) Clock Frequency
    31. 8.31 USCI (UART Mode)
    32. 8.32 USCI (SPI Master Mode) Clock Frequency
    33. 8.33 USCI (SPI Master Mode)
    34. 8.34 USCI (SPI Slave Mode)
    35. 8.35 USCI (I2C Mode)
    36. 8.36 12-Bit ADC, Power Supply and Input Range Conditions
    37. 8.37 12-Bit ADC, Timing Parameters
    38. 8.38 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage
    39. 8.39 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
    40. 8.40 12-Bit ADC, Temperature Sensor and Built-In VMID
    41. 8.41 REF, External Reference
    42. 8.42 REF, Built-In Reference
    43. 8.43 Flash Memory
    44. 8.44 JTAG and Spy-Bi-Wire Interface
  9. Detailed Description
    1. 9.1  CPU
    2. 9.2  Operating Modes
    3. 9.3  Interrupt Vector Addresses
    4. 9.4  Memory Organization
    5. 9.5  Bootloader (BSL)
    6. 9.6  JTAG Operation
      1. 9.6.1 JTAG Standard Interface
      2. 9.6.2 Spy-Bi-Wire Interface
    7. 9.7  Flash Memory
    8. 9.8  RAM
    9. 9.9  Peripherals
      1. 9.9.1  Digital I/O
      2. 9.9.2  Oscillator and System Clock
      3. 9.9.3  Power-Management Module (PMM)
      4. 9.9.4  Hardware Multiplier (MPY)
      5. 9.9.5  Real-Time Clock (RTC_A)
      6. 9.9.6  Watchdog Timer (WDT_A)
      7. 9.9.7  System Module (SYS)
      8. 9.9.8  DMA Controller
      9. 9.9.9  Universal Serial Communication Interface (USCI)
      10. 9.9.10 TA0
      11. 9.9.11 TA1
      12. 9.9.12 TB0
      13. 9.9.13 ADC12_A
      14. 9.9.14 CRC16
      15. 9.9.15 Reference (REF) Module Voltage Reference
      16. 9.9.16 Embedded Emulation Module (EEM) (L Version)
      17. 9.9.17 Peripheral File Map
    10. 9.10 Input/Output Diagrams
      1. 9.10.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 9.10.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 9.10.3  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 9.10.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 9.10.5  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      6. 9.10.6  Port P5 (P5.2 and P5.3) Input/Output With Schmitt Trigger
      7. 9.10.7  Port P5 (P5.4 to P5.7) Input/Output With Schmitt Trigger
      8. 9.10.8  Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      9. 9.10.9  Port P7 (P7.0 and P7.1) Input/Output With Schmitt Trigger
      10. 9.10.10 Port P7 (P7.2 and P7.3) Input/Output With Schmitt Trigger
      11. 9.10.11 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
      12. 9.10.12 Port P8 (P8.0 to P8.7) Input/Output With Schmitt Trigger
      13. 9.10.13 Port P9 (P9.0 to P9.7) Input/Output With Schmitt Trigger
      14. 9.10.14 Port P10 (P10.0 to P10.7) Input/Output With Schmitt Trigger
      15. 9.10.15 Port P11 (P11.0 to P11.2) Input/Output With Schmitt Trigger
      16. 9.10.16 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      17. 9.10.17 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    11. 9.11 Device Descriptors
  10. 10Device and Documentation Support
    1. 10.1  Getting Started
    2. 10.2  Device Nomenclature
    3. 10.3  Tools and Software
    4. 10.4  Documentation Support
    5. 10.5  Related Links
    6. 10.6  Support Resources
    7. 10.7  Trademarks
    8. 10.8  Electrostatic Discharge Caution
    9. 10.9  Export Control Notice
    10. 10.10 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Device Descriptors

Table 9-59 shows the contents of the device descriptor tag-length-value (TLV) structure for each device type.

Table 9-59 Device Descriptors
DESCRIPTION(1)ADDRESSSIZE
(bytes)
VALUE
F5438AF5437AF5436AF5435AF5419AF5418A
Info BlockInfo length01A00h106h06h06h06h06h06h
CRC length01A01h106h06h06h06h06h06h
CRC value01A02h2Per unitPer unitPer unitPer unitPer unitPer unit
Device ID01A04h105h04h03h02h01h00h
Device ID01A05h180h80h80h80h80h80h
Hardware revision01A06h1Per unitPer unitPer unitPer unitPer unitPer unit
Firmware revision01A07h1Per unitPer unitPer unitPer unitPer unitPer unit
Die RecordDie record tag01A08h108h08h08h08h08h08h
Die record length01A09h10Ah0Ah0Ah0Ah0Ah0Ah
Lot/wafer ID01A0Ah4Per unitPer unitPer unitPer unitPer unitPer unit
Die X position01A0Eh2Per unitPer unitPer unitPer unitPer unitPer unit
Die Y position01A10h2Per unitPer unitPer unitPer unitPer unitPer unit
Test results01A12h2Per unitPer unitPer unitPer unitPer unitPer unit
ADC12 CalibrationADC12 calibration tag01A14h111h11h11h11h11h11h
ADC12 calibration length01A15h110h10h10h10h10h10h
ADC gain factor01A16h2Per unitPer unitPer unitPer unitPer unitPer unit
ADC offset01A18h2Per unitPer unitPer unitPer unitPer unitPer unit
ADC 1.5-V reference
Temperature sensor 30°C
01A1Ah2Per unitPer unitPer unitPer unitPer unitPer unit
ADC 1.5-V reference
Temperature sensor 85°C
01A1Ch2Per unitPer unitPer unitPer unitPer unitPer unit
ADC 2.0-V reference
Temperature sensor 30°C
01A1Eh2Per unitPer unitPer unitPer unitPer unitPer unit
ADC 2.0-V reference
Temperature sensor 85°C
01A20h2Per unitPer unitPer unitPer unitPer unitPer unit
ADC 2.5-V reference
Temperature sensor 30°C
01A22h2Per unitPer unitPer unitPer unitPer unitPer unit
ADC 2.5-V reference
Temperature sensor 85°C
01A24h2Per unitPer unitPer unitPer unitPer unitPer unit
REF CalibrationREF calibration tag01A26h112h12h12h12h12h12h
REF calibration length01A27h106h06h06h06h06h06h
REF 1.5-V reference01A28h2Per unitPer unitPer unitPer unitPer unitPer unit
REF 2.0-V reference01A2Ah2Per unitPer unitPer unitPer unitPer unitPer unit
REF 2.5-V reference01A2Ch2Per unitPer unitPer unitPer unitPer unitPer unit
Peripheral DescriptorPeripheral descriptor tag01A2Eh102h02h02h02h02h02h
Peripheral descriptor length01A2Fh161h059h62h5Ah61h59h
Memory 1208h
8Ah
08h
8Ah
08h
8Ah
08h
8Ah
08h
8Ah
08h
8Ah
Memory 220Ch
86h
0Ch
86h
0Ch
86h
0Ch
86h
0Ch
86h
0Ch
86h
Memory 320Eh
30h
0Eh
30h
0Eh
30h
0Eh
30h
0Eh
30h
0Eh
30h
Memory 422Eh
98h
2Eh
98h
2Eh
97h
2Eh
97h
2Eh
96h
2Eh
96h
Memory 50/1N/AN/A94h94hN/AN/A
Delimiter100h00h00h00h00h00h
Peripheral count121h1Dh21h1Dh21h1Dh
MSP430CPUXV2200h
23h
00h
23h
00h
23h
00h
23h
00h
23h
00h
23h
SBW200h
0Fh
00h
0Fh
00h
0Fh
00h
0Fh
00h
0Fh
00h
0Fh
EEM-8200h
05h
00h
05h
00h
05h
00h
05h
00h
05h
00h
05h
TI BSL200h
FCh
00h
FCh
00h
FCh
00h
FCh
00h
FCh
00h
FCh
Package200h
1Fh
00h
1Fh
00h
1Fh
00h
1Fh
00h
1Fh
00h
1Fh
SFR210h
41h
10h
41h
10h
41h
10h
41h
10h
41h
10h
41h
PMM202h
30h
02h
30h
02h
30h
02h
30h
02h
30h
02h
30h
FCTL202h
38h
02h
38h
02h
38h
02h
38h
02h
38h
02h
38h
CRC16 straight201h
3Ch
01h
3Ch
01h
3Ch
01h
3Ch
01h
3Ch
01h
3Ch
CRC16 bit reversed200h
3Dh
00h
3Dh
00h
3Dh
00h
3Dh
00h
3Dh
00h
3Dh
RAMCTL200h
44h
00h
44h
00h
44h
00h
44h
00h
44h
00h
44h
WDT_A200h
40h
00h
40h
00h
40h
00h
40h
00h
40h
00h
40h
UCS201h
48h
01h
48h
01h
48h
01h
48h
01h
48h
01h
48h
SYS202h
42h
02h
42h
02h
42h
02h
42h
02h
42h
02h
42h
REF203h
A0h
03h
A0h
03h
A0h
03h
A0h
03h
A0h
03h
A0h
Port 1 and 2205h
51h
05h
51h
05h
51h
05h
51h
05h
51h
05h
51h
Port 3 and 4202h
52h
02h
52h
02h
52h
02h
52h
02h
52h
02h
52h
Port 5 and 6202h
53h
02h
53h
02h
53h
02h
53h
02h
53h
02h
53h
Port 7 and 8202h
54h
02h
54h
02h
54h
02h
54h
02h
54h
02h
54h
Port 9 and 10202h
55h
N/A02h
55h
N/A02h
55h
N/A
Port 11 and 12202h
56h
N/A02h
56h
N/A02h
56h
N/A
Peripheral Descriptor (continued)JTAG208h
5Fh
0Ch
5Fh
08h
5Fh
0Ch
5Fh
08h
5Fh
0Ch
5Fh
TA0202h
62h
02h
62h
02h
62h
02h
62h
02h
62h
02h
62h
TA1204h
61h
04h
61h
04h
61h
04h
61h
04h
61h
04h
61h
TB0204h
67h
04h
67h
04h
67h
04h
67h
04h
67h
04h
67h
RTC20Eh
68h
0Eh
68h
0Eh
68h
0Eh
68h
0Eh
68h
0Eh
68h
MPY32202h
85h
02h
85h
02h
85h
02h
85h
02h
85h
02h
85h
DMA-3204h
47h
04h
47h
04h
47h
04h
47h
04h
47h
04h
47h
USCI_A and USCI_B20Ch
90h
0Ch
90h
0Ch
90h
0Ch
90h
0Ch
90h
0Ch
90h
USCI_A and USCI_B204h
90h
04h
90h
04h
90h
04h
90h
04h
90h
04h
90h
USCI_A and USCI_B204h
90h
N/A04h
90h
N/A04h
90h
N/A
USCI_A and USCI_B204h
90h
N/A04h
90h
N/A04h
90h
N/A
ADC12_A208h
D1h
10h
D1h
08h
D1h
10h
D1h
08h
D1h
10h
D1h
InterruptsTB0.CCIFG0164h64h64h64h64h64h
TB0.CCIFG1..6165h65h65h65h65h65h
WDTIFG140h40h40h40h40h40h
USCI_A0190h90h90h90h90h90h
USCI_B0191h91h91h91h91h91h
ADC12_A1D0hD0hD0hD0hD0hD0h
TA0.CCIFG0160h60h60h60h60h60h
TA0.CCIFG1..4161h61h61h61h61h61h
USCI_A2194h01h94h01h94h01h
USCI_B2195h01h95h01h95h01h
DMA146h46h46h46h46h46h
TA1.CCIFG0162h62h62h62h62h62h
TA1.CCIFG1..2163h63h63h63h63h63h
P1150h50h50h50h50h50h
USCI_A1192h92h92h92h92h92h
USCI_B1193h93h93h93h93h93h
USCI_A3196h01h96h01h96h01h
USCI_B3197h01h97h01h97h01h
P2151h51h51h51h51h51h
RTC_A168h68h68h68h68h68h
Delimiter100h00h00h00h00h00h
N/A = Not applicable