SLAS700D October   2012  – September 2018 MSP430F5358 , MSP430F5359 , MSP430F5658 , MSP430F5659 , MSP430F6458 , MSP430F6459 , MSP430F6658 , MSP430F6659

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagrams
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    7. 5.7  Thermal Resistance Characteristics
    8. 5.8  Schmitt-Trigger Inputs – General-Purpose I/O
    9. 5.9  Inputs – Ports P1, P2, P3, and P4
    10. 5.10 Leakage Current – General-Purpose I/O
    11. 5.11 Outputs – General-Purpose I/O (Full Drive Strength)
    12. 5.12 Outputs – General-Purpose I/O (Reduced Drive Strength)
    13. 5.13 Output Frequency – Ports P1, P2, and P3
    14. 5.14 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    15. 5.15 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    16. 5.16 Crystal Oscillator, XT1, Low-Frequency Mode
    17. 5.17 Crystal Oscillator, XT2
    18. 5.18 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    19. 5.19 Internal Reference, Low-Frequency Oscillator (REFO)
    20. 5.20 DCO Frequency
    21. 5.21 PMM, Brownout Reset (BOR)
    22. 5.22 PMM, Core Voltage
    23. 5.23 PMM, SVS High Side
    24. 5.24 PMM, SVM High Side
    25. 5.25 PMM, SVS Low Side
    26. 5.26 PMM, SVM Low Side
    27. 5.27 Wake-up Times From Low-Power Modes
    28. 5.28 Timer_A – Timers TA0, TA1, and TA2
    29. 5.29 Timer_B – Timer TB0
    30. 5.30 Battery Backup
    31. 5.31 USCI (UART Mode)
    32. 5.32 USCI (SPI Master Mode)
    33. 5.33 USCI (SPI Slave Mode)
    34. 5.34 USCI (I2C Mode)
    35. 5.35 LCD_B Operating Characteristics
    36. 5.36 LCD_B Electrical Characteristics
    37. 5.37 12-Bit ADC, Power Supply and Input Range Conditions
    38. 5.38 12-Bit ADC, Timing Parameters
    39. 5.39 12-Bit ADC, Linearity Parameters Using an External Reference Voltage
    40. 5.40 12-Bit ADC, Linearity Parameters Using AVCC as Reference Voltage
    41. 5.41 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
    42. 5.42 12-Bit ADC, Temperature Sensor and Built-In VMID
    43. 5.43 REF, External Reference
    44. 5.44 REF, Built-In Reference
    45. 5.45 12-Bit DAC, Supply Specifications
    46. 5.46 12-Bit DAC, Linearity Specifications
    47. 5.47 12-Bit DAC, Output Specifications
    48. 5.48 12-Bit DAC, Reference Input Specifications
    49. 5.49 12-Bit DAC, Dynamic Specifications
    50. 5.50 12-Bit DAC, Dynamic Specifications (Continued)
    51. 5.51 Comparator_B
    52. 5.52 Ports PU.0 and PU.1
    53. 5.53 USB Output Ports DP and DM
    54. 5.54 USB Input Ports DP and DM
    55. 5.55 USB-PWR (USB Power System)
    56. 5.56 USB-PLL (USB Phase Locked Loop)
    57. 5.57 Flash Memory
    58. 5.58 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  CPU (Link to User's Guide)
    2. 6.2  Instruction Set
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Memory Organization
    6. 6.6  Bootloader (BSL)
      1. 6.6.1 USB BSL
      2. 6.6.2 UART BSL
    7. 6.7  JTAG Operation
      1. 6.7.1 JTAG Standard Interface
      2. 6.7.2 Spy-Bi-Wire Interface
    8. 6.8  Flash Memory (Link to User's Guide)
    9. 6.9  Memory Integrity Detection (MID) (Link to User's Guide)
    10. 6.10 RAM (Link to User's Guide)
    11. 6.11 Backup RAM (Link to User's Guide)
    12. 6.12 Peripherals
      1. 6.12.1  Digital I/O (Link to User's Guide)
      2. 6.12.2  Port Mapping Controller (Link to User's Guide)
      3. 6.12.3  Oscillator and System Clock (Link to User's Guide)
      4. 6.12.4  Power-Management Module (PMM) (Link to User's Guide)
      5. 6.12.5  Hardware Multiplier (MPY) (Link to User's Guide)
      6. 6.12.6  Real-Time Clock (RTC_B) (Link to User's Guide)
      7. 6.12.7  Watchdog Timer (WDT_A) (Link to User's Guide)
      8. 6.12.8  System Module (SYS) (Link to User's Guide)
      9. 6.12.9  DMA Controller (Link to User's Guide)
      10. 6.12.10 Universal Serial Communication Interface (USCI) (Links to User's Guide: UART Mode, SPI Mode, I2C Mode)
      11. 6.12.11 Timer TA0 (Link to User's Guide)
      12. 6.12.12 Timer TA1 (Link to User's Guide)
      13. 6.12.13 Timer TA2 (Link to User's Guide)
      14. 6.12.14 Timer TB0 (Link to User's Guide)
      15. 6.12.15 Comparator_B (Link to User's Guide)
      16. 6.12.16 ADC12_A (Link to User's Guide)
      17. 6.12.17 DAC12_A (Link to User's Guide)
      18. 6.12.18 CRC16 (Link to User's Guide)
      19. 6.12.19 Voltage Reference (REF) Module (Link to User's Guide)
      20. 6.12.20 LCD_B (Link to User's Guide)
      21. 6.12.21 USB Universal Serial Bus (Link to User's Guide)
      22. 6.12.22 LDO and PU Port
      23. 6.12.23 Embedded Emulation Module (EEM) (L Version) (Link to User's Guide)
      24. 6.12.24 Peripheral File Map
    13. 6.13 Input/Output Diagrams
      1. 6.13.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 6.13.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 6.13.3  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 6.13.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 6.13.5  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      6. 6.13.6  Port P5 (P5.2 to P5.7) Input/Output With Schmitt Trigger
      7. 6.13.7  Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      8. 6.13.8  Port P7 (P7.2) Input/Output With Schmitt Trigger
      9. 6.13.9  Port P7 (P7.3) Input/Output With Schmitt Trigger
      10. 6.13.10 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
      11. 6.13.11 Port P8 (P8.0 to P8.7) Input/Output With Schmitt Trigger
      12. 6.13.12 Port P9 (P9.0 to P9.7) Input/Output With Schmitt Trigger
      13. 6.13.13 Port PU (PU.0/DP, PU.1/DM, PUR) USB Ports (F665x, F565x)
      14. 6.13.14 Port PU (PU.0 and PU.1) Ports (F645x, F535x)
      15. 6.13.15 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      16. 6.13.16 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    14. 6.14 Device Descriptors
  7. 7Device and Documentation Support
    1. 7.1  Getting Started and Next Steps
    2. 7.2  Device Nomenclature
    3. 7.3  Tools and Software
    4. 7.4  Documentation Support
    5. 7.5  Related Links
    6. 7.6  Community Resources
    7. 7.7  Trademarks
    8. 7.8  Electrostatic Discharge Caution
    9. 7.9  Export Control Notice
    10. 7.10 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12-Bit DAC, Linearity Specifications

See Figure 5-17, over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Resolution 12-bit monotonic 12 bits
INL Integral nonlinearity(1) VeREF+ = 1.5 V, DAC12AMPx = 7, DAC12IR = 1 2.2 V ±2 ±4 LSB
VeREF+ = 2.5 V, DAC12AMPx = 7, DAC12IR = 1 3 V ±2 ±4
DNL Differential nonlinearity(1) VeREF+ = 1.5 V, DAC12AMPx = 7, DAC12IR = 1 2.2 V ±0.4 ±1 LSB
VeREF+ = 2.5 V, DAC12AMPx = 7, DAC12IR = 1 3 V ±0.4 ±1
EO Offset voltage Without calibration(1)(2) VeREF+ = 1.5 V,
DAC12AMPx = 7,
DAC12IR = 1
2.2 V ±21 mV
VeREF+ = 2.5 V,
DAC12AMPx = 7,
DAC12IR = 1
3 V ±21
With calibration(1)(2) VeREF+ = 1.5 V,
DAC12AMPx = 7,
DAC12IR = 1
2.2 V ±1.5
VeREF+ = 2.5 V,
DAC12AMPx = 7,
DAC12IR = 1
3 V ±1.5
dE(O)/dT Offset error temperature coefficient(1) With calibration 2.2 V, 3 V ±10 µV/°C
EG Gain error VeREF+ = 1.5 V 2.2 V ±2.5 %FSR
VeREF+ = 2.5 V 3 V ±2.5
dE(G)/dT Gain temperature coefficient(1) 2.2 V, 3 V 10 ppm of FSR/°C
tOffset_Cal Time for offset calibration(3) DAC12AMPx = 2 2.2 V, 3 V 165 ms
DAC12AMPx = 3, 5 66
DAC12AMPx = 4, 6, 7 16.5
Parameters calculated from the best-fit curve from 0x0F to 0xFFF. The best-fit curve method is used to deliver coefficients “a” and “b” of the first-order equation: y = a + bx. VDAC12_xOUT = EO + (1 + EG) × (VeREF+/4095) × DAC12_xDAT, DAC12IR = 1.
The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON
The offset calibration can be done if DAC12AMPx = \{2, 3, 4, 5, 6, 7\}. The output operational amplifier is switched off with DAC12AMPx = \{0, 1\}. TI recommends configuring the DAC12 module before initiating calibration. Port activity during calibration may affect accuracy and is not recommended.
MSP430F6659 MSP430F6658 MSP430F6459 MSP430F6458 MSP430F5659 MSP430F5658 MSP430F5359 MSP430F5358 slau208dac12a-101.gifFigure 5-17 Linearity Test Load Conditions and Gain/Offset Definition