SLAS700D October   2012  – September 2018 MSP430F5358 , MSP430F5359 , MSP430F5658 , MSP430F5659 , MSP430F6458 , MSP430F6459 , MSP430F6658 , MSP430F6659

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagrams
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    7. 5.7  Thermal Resistance Characteristics
    8. 5.8  Schmitt-Trigger Inputs – General-Purpose I/O
    9. 5.9  Inputs – Ports P1, P2, P3, and P4
    10. 5.10 Leakage Current – General-Purpose I/O
    11. 5.11 Outputs – General-Purpose I/O (Full Drive Strength)
    12. 5.12 Outputs – General-Purpose I/O (Reduced Drive Strength)
    13. 5.13 Output Frequency – Ports P1, P2, and P3
    14. 5.14 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    15. 5.15 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    16. 5.16 Crystal Oscillator, XT1, Low-Frequency Mode
    17. 5.17 Crystal Oscillator, XT2
    18. 5.18 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    19. 5.19 Internal Reference, Low-Frequency Oscillator (REFO)
    20. 5.20 DCO Frequency
    21. 5.21 PMM, Brownout Reset (BOR)
    22. 5.22 PMM, Core Voltage
    23. 5.23 PMM, SVS High Side
    24. 5.24 PMM, SVM High Side
    25. 5.25 PMM, SVS Low Side
    26. 5.26 PMM, SVM Low Side
    27. 5.27 Wake-up Times From Low-Power Modes
    28. 5.28 Timer_A – Timers TA0, TA1, and TA2
    29. 5.29 Timer_B – Timer TB0
    30. 5.30 Battery Backup
    31. 5.31 USCI (UART Mode)
    32. 5.32 USCI (SPI Master Mode)
    33. 5.33 USCI (SPI Slave Mode)
    34. 5.34 USCI (I2C Mode)
    35. 5.35 LCD_B Operating Characteristics
    36. 5.36 LCD_B Electrical Characteristics
    37. 5.37 12-Bit ADC, Power Supply and Input Range Conditions
    38. 5.38 12-Bit ADC, Timing Parameters
    39. 5.39 12-Bit ADC, Linearity Parameters Using an External Reference Voltage
    40. 5.40 12-Bit ADC, Linearity Parameters Using AVCC as Reference Voltage
    41. 5.41 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
    42. 5.42 12-Bit ADC, Temperature Sensor and Built-In VMID
    43. 5.43 REF, External Reference
    44. 5.44 REF, Built-In Reference
    45. 5.45 12-Bit DAC, Supply Specifications
    46. 5.46 12-Bit DAC, Linearity Specifications
    47. 5.47 12-Bit DAC, Output Specifications
    48. 5.48 12-Bit DAC, Reference Input Specifications
    49. 5.49 12-Bit DAC, Dynamic Specifications
    50. 5.50 12-Bit DAC, Dynamic Specifications (Continued)
    51. 5.51 Comparator_B
    52. 5.52 Ports PU.0 and PU.1
    53. 5.53 USB Output Ports DP and DM
    54. 5.54 USB Input Ports DP and DM
    55. 5.55 USB-PWR (USB Power System)
    56. 5.56 USB-PLL (USB Phase Locked Loop)
    57. 5.57 Flash Memory
    58. 5.58 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  CPU (Link to User's Guide)
    2. 6.2  Instruction Set
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Memory Organization
    6. 6.6  Bootloader (BSL)
      1. 6.6.1 USB BSL
      2. 6.6.2 UART BSL
    7. 6.7  JTAG Operation
      1. 6.7.1 JTAG Standard Interface
      2. 6.7.2 Spy-Bi-Wire Interface
    8. 6.8  Flash Memory (Link to User's Guide)
    9. 6.9  Memory Integrity Detection (MID) (Link to User's Guide)
    10. 6.10 RAM (Link to User's Guide)
    11. 6.11 Backup RAM (Link to User's Guide)
    12. 6.12 Peripherals
      1. 6.12.1  Digital I/O (Link to User's Guide)
      2. 6.12.2  Port Mapping Controller (Link to User's Guide)
      3. 6.12.3  Oscillator and System Clock (Link to User's Guide)
      4. 6.12.4  Power-Management Module (PMM) (Link to User's Guide)
      5. 6.12.5  Hardware Multiplier (MPY) (Link to User's Guide)
      6. 6.12.6  Real-Time Clock (RTC_B) (Link to User's Guide)
      7. 6.12.7  Watchdog Timer (WDT_A) (Link to User's Guide)
      8. 6.12.8  System Module (SYS) (Link to User's Guide)
      9. 6.12.9  DMA Controller (Link to User's Guide)
      10. 6.12.10 Universal Serial Communication Interface (USCI) (Links to User's Guide: UART Mode, SPI Mode, I2C Mode)
      11. 6.12.11 Timer TA0 (Link to User's Guide)
      12. 6.12.12 Timer TA1 (Link to User's Guide)
      13. 6.12.13 Timer TA2 (Link to User's Guide)
      14. 6.12.14 Timer TB0 (Link to User's Guide)
      15. 6.12.15 Comparator_B (Link to User's Guide)
      16. 6.12.16 ADC12_A (Link to User's Guide)
      17. 6.12.17 DAC12_A (Link to User's Guide)
      18. 6.12.18 CRC16 (Link to User's Guide)
      19. 6.12.19 Voltage Reference (REF) Module (Link to User's Guide)
      20. 6.12.20 LCD_B (Link to User's Guide)
      21. 6.12.21 USB Universal Serial Bus (Link to User's Guide)
      22. 6.12.22 LDO and PU Port
      23. 6.12.23 Embedded Emulation Module (EEM) (L Version) (Link to User's Guide)
      24. 6.12.24 Peripheral File Map
    13. 6.13 Input/Output Diagrams
      1. 6.13.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 6.13.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 6.13.3  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 6.13.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 6.13.5  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      6. 6.13.6  Port P5 (P5.2 to P5.7) Input/Output With Schmitt Trigger
      7. 6.13.7  Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      8. 6.13.8  Port P7 (P7.2) Input/Output With Schmitt Trigger
      9. 6.13.9  Port P7 (P7.3) Input/Output With Schmitt Trigger
      10. 6.13.10 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
      11. 6.13.11 Port P8 (P8.0 to P8.7) Input/Output With Schmitt Trigger
      12. 6.13.12 Port P9 (P9.0 to P9.7) Input/Output With Schmitt Trigger
      13. 6.13.13 Port PU (PU.0/DP, PU.1/DM, PUR) USB Ports (F665x, F565x)
      14. 6.13.14 Port PU (PU.0 and PU.1) Ports (F645x, F535x)
      15. 6.13.15 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      16. 6.13.16 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    14. 6.14 Device Descriptors
  7. 7Device and Documentation Support
    1. 7.1  Getting Started and Next Steps
    2. 7.2  Device Nomenclature
    3. 7.3  Tools and Software
    4. 7.4  Documentation Support
    5. 7.5  Related Links
    6. 7.6  Community Resources
    7. 7.7  Trademarks
    8. 7.8  Electrostatic Discharge Caution
    9. 7.9  Export Control Notice
    10. 7.10 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Port Mapping Controller (Link to User's Guide)

The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P2. Table 6-10 lists the available mappings, and Table 6-11 lists the default settings.

Table 6-10 Port Mapping Mnemonics and Functions

VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION
0 PM_NONE None DVSS
1 PM_CBOUT Comparator_B output
PM_TB0CLK Timer TB0 clock input
2 PM_ADC12CLK ADC12CLK
PM_DMAE0 DMAE0 Input
3 PM_SVMOUT SVM output
PM_TB0OUTH Timer TB0 high impedance input TB0OUTH
4 PM_TB0CCR0B Timer TB0 CCR0 capture input CCI0B Timer TB0: TB0.0 compare output Out0
5 PM_TB0CCR1B Timer TB0 CCR1 capture input CCI1B Timer TB0: TB0.1 compare output Out1
6 PM_TB0CCR2B Timer TB0 CCR2 capture input CCI2B Timer TB0: TB0.2 compare output Out2
7 PM_TB0CCR3B Timer TB0 CCR3 capture input CCI3B Timer TB0: TB0.3 compare output Out3
8 PM_TB0CCR4B Timer TB0 CCR4 capture input CCI4B Timer TB0: TB0.4 compare output Out4
9 PM_TB0CCR5B Timer TB0 CCR5 capture input CCI5B Timer TB0: TB0.5 compare output Out5
10 PM_TB0CCR6B Timer TB0 CCR6 capture input CCI6B Timer TB0: TB0.6 compare output Out6
11 PM_UCA0RXD USCI_A0 UART RXD (Direction controlled by USCI – input)
PM_UCA0SOMI USCI_A0 SPI slave out master in (direction controlled by USCI)
12 PM_UCA0TXD USCI_A0 UART TXD (Direction controlled by USCI – output)
PM_UCA0SIMO USCI_A0 SPI slave in master out (direction controlled by USCI)
13 PM_UCA0CLK USCI_A0 clock input/output (direction controlled by USCI)
PM_UCB0STE USCI_B0 SPI slave transmit enable (direction controlled by USCI – input)
14 PM_UCB0SOMI USCI_B0 SPI slave out master in (direction controlled by USCI)
PM_UCB0SCL USCI_B0 I2C clock (open drain and direction controlled by USCI)
15 PM_UCB0SIMO USCI_B0 SPI slave in master out (direction controlled by USCI)
PM_UCB0SDA USCI_B0 I2C data (open drain and direction controlled by USCI)
16 PM_UCB0CLK USCI_B0 clock input/output (direction controlled by USCI)
PM_UCA0STE USCI_A0 SPI slave transmit enable (direction controlled by USCI – input)
17 PM_MCLK MCLK
18 Reserved Reserved for test purposes. Do not use this setting.
19 Reserved Reserved for test purposes. Do not use this setting.
20-30 Reserved None DVSS
31 (0FFh)(1) PM_ANALOG Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents when applying analog signals.
The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide, and the upper bits are ignored, which results in a read value of 31.

Table 6-11 Default Mapping

PIN PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION
P2.0/P2MAP0 PM_UCB0STE,
PM_UCA0CLK

USCI_B0 SPI slave transmit enable (direction controlled by USCI – input),

USCI_A0 clock input/output (direction controlled by USCI)

P2.1/P2MAP1 PM_UCB0SIMO,
PM_UCB0SDA

USCI_B0 SPI slave in master out (direction controlled by USCI),

USCI_B0 I2C data (open drain and direction controlled by USCI)

P2.2/P2MAP2 PM_UCB0SOMI,
PM_UCB0SCL

USCI_B0 SPI slave out master in (direction controlled by USCI),

USCI_B0 I2C clock (open drain and direction controlled by USCI)

P2.3/P2MAP3 PM_UCB0CLK,
PM_UCA0STE

USCI_B0 clock input/output (direction controlled by USCI),

USCI_A0 SPI slave transmit enable (direction controlled by USCI – input)

P2.4/P2MAP4 PM_UCA0TXD,
PM_UCA0SIMO

USCI_A0 UART TXD (direction controlled by USCI – output),

USCI_A0 SPI slave in master out (direction controlled by USCI)

P2.5/P2MAP5 PM_UCA0RXD,
PM_UCA0SOMI

USCI_A0 UART RXD (direction controlled by USCI – input),

USCI_A0 SPI slave out master in (direction controlled by USCI)

P2.6/P2MAP6/ R03 PM_NONE DVSS
P2.7/P2MAP7/LCDREF/R13 PM_NONE DVSS