SLAS380D April   2004  – November 2014 MSP430FG437 , MSP430FG438 , MSP430FG439

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3 Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Handling Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Supply Current Into AVCC + DVCC Excluding External Current
    5. 5.5  Schmitt-Trigger Inputs - Ports P1 to P6, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)
    6. 5.6  Inputs Px.y, TAx, TBx
    7. 5.7  Leakage Current - Ports P1 to P6
    8. 5.8  Outputs - Ports P1 to P6
    9. 5.9  Output Frequency
    10. 5.10 Typical Characteristics - Outputs
    11. 5.11 Wake-Up From LPM3
    12. 5.12 RAM
    13. 5.13 LCD
    14. 5.14 Comparator_A
    15. 5.15 Comparator_A Typical Characteristics
    16. 5.16 Power-On Reset (POR) and Brownout Reset (BOR)
    17. 5.17 Supply Voltage Supervisor (SVS) and Supply Voltage Monitor (SVM)
    18. 5.18 DCO
    19. 5.19 Crystal Oscillator, XT1 Oscillator
    20. 5.20 Crystal Oscillator, XT2 Oscillator
    21. 5.21 USART0
    22. 5.22 12-Bit ADC, Power Supply and Input Range Conditions
    23. 5.23 12-Bit ADC, External Reference
    24. 5.24 12-Bit ADC, Built-In Reference
    25. 5.25 12-Bit ADC, Timing Parameters
    26. 5.26 12-Bit ADC, Linearity Parameters
    27. 5.27 12-Bit ADC, Temperature Sensor and Built-In VMID
    28. 5.28 12-Bit DAC, Supply Specifications
    29. 5.29 12-Bit DAC, Linearity Specifications
    30. 5.30 12-Bit DAC, Output Specifications
    31. 5.31 12-Bit DAC, Reference Input Specifications
    32. 5.32 12-Bit DAC, Dynamic Specifications
    33. 5.33 12-Bit DAC, Dynamic Specifications (Continued)
    34. 5.34 Operational Amplifier (OA), Supply Specifications
    35. 5.35 Operational Amplifier (OA), Input/Output Specifications
    36. 5.36 Operational Amplifier (OA), Dynamic Specifications
    37. 5.37 OA Dynamic Specifications Typical Characteristics
    38. 5.38 Flash Memory
    39. 5.39 JTAG Interface
    40. 5.40 JTAG Fuse
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Instruction Set
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Special Function Registers (SFRs)
      1. 6.5.1 Interrupt Enable Registers 1 and 2
      2. 6.5.2 Interrupt Flag Registers 1 and 2
      3. 6.5.3 Module Enable Registers 1 and 2
    6. 6.6  Memory Organization
    7. 6.7  Bootstrap Loader (BSL)
    8. 6.8  Flash Memory
    9. 6.9  Peripherals
      1. 6.9.1  DMA Controller
      2. 6.9.2  Oscillator and System Clock
      3. 6.9.3  Brownout, Supply Voltage Supervisor
      4. 6.9.4  Digital I/O
      5. 6.9.5  Basic Timer1
      6. 6.9.6  LCD Drive
      7. 6.9.7  OA
      8. 6.9.8  Watchdog Timer (WDT)
      9. 6.9.9  USART0
      10. 6.9.10 Timer_A3
      11. 6.9.11 Timer_B3
      12. 6.9.12 Comparator_A
      13. 6.9.13 ADC12
      14. 6.9.14 DAC12
      15. 6.9.15 Peripheral File Map
    10. 6.10 Input/Output Schematics
      1. 6.10.1  Port P1, P1.0 to P1.5, Input/Output With Schmitt Trigger
      2. 6.10.2  Port P1, P1.6 and P1.7, Input/Output With Schmitt Trigger
      3. 6.10.3  Port P2, P2.0 and P2.4 to P2.5, Input/Output With Schmitt Trigger
      4. 6.10.4  Port P2, P2.1 to P2.3, Input/Output With Schmitt Trigger
      5. 6.10.5  Port P2, P2.6 and P2.7, Input/Output With Schmitt Trigger
      6. 6.10.6  Port P3, P3.0 to P3.3, Input/Output With Schmitt Trigger
      7. 6.10.7  Port P3, P3.4 to P3.7, Input/Output With Schmitt Trigger
      8. 6.10.8  Port P4, P4.0 to P4.5, Input/Output With Schmitt Trigger
      9. 6.10.9  Port P4, P4.6, Input/Output With Schmitt Trigger
      10. 6.10.10 Port P4, P4.7, Input/Output With Schmitt Trigger
      11. 6.10.11 Port P5, P5.0, Input/Output With Schmitt Trigger
      12. 6.10.12 Port P5, P5.1, Input/Output With Schmitt Trigger
      13. 6.10.13 Port P5, P5.2 to P5.4, Input/Output With Schmitt Trigger
      14. 6.10.14 Port P5, P5.5 to P5.7, Input/Output With Schmitt Trigger
      15. 6.10.15 Port P6, P6.0, P6.2, and P6.4, Input/Output With Schmitt Trigger
      16. 6.10.16 Port P6, P6.1, Input/Output With Schmitt Trigger
      17. 6.10.17 Port P6, P6.3, Input/Output With Schmitt Trigger
      18. 6.10.18 Port P6, P6.5, Input/Output With Schmitt Trigger
      19. 6.10.19 Port P6, P6.6, Input/Output With Schmitt Trigger
      20. 6.10.20 Port P6, P6.7, Input/Output With Schmitt Trigger
      21. 6.10.21 VeREF+/DAC0
      22. 6.10.22 JTAG Pins TMS, TCK, TDI/TCLK, TDO/TDI, Input/Output With Schmitt Trigger or Output
      23. 6.10.23 JTAG Fuse Check Mode
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Development Support
        1. 7.1.1.1 Development Kit
      2. 7.1.2 Device and Development Tool Nomenclature
    2. 7.2 Documentation Support
      1. 7.2.1 Related Links
      2. 7.2.2 Community Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Detailed Description

6.1 CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions.

slas508_RISCarch.gif

6.2 Instruction Set

The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data. Table 6-1 shows examples of the three types of instruction formats; Table 6-2 lists the address modes.

Table 6-1 Instruction Word Formats

INSTRUCTION FORMAT EXAMPLE OPERATION
Dual operands, source-destination ADD R4,R5 R4 + R5 → R5
Single operands, destination only CALL R8 PC→(TOS), R8 →PC
Relative jump, un/conditional JNE Jump-on-equal bit = 0

Table 6-2 Address Mode Descriptions

ADDRESS MODE S(1) D(1) SYNTAX EXAMPLE OPERATION
Register ✓ ✓ MOV Rs,Rd MOV R10,R11 R10 → R11
Indexed ✓ ✓ MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)→ M(6+R6)
Symbolic (PC relative) ✓ ✓ MOV EDE,TONI M(EDE) → M(TONI)
Absolute ✓ ✓ MOV & MEM, & TCDAT M(MEM) → M(TCDAT)
Indirect ✓ MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) → M(Tab+R6)
Indirect autoincrement ✓ MOV @Rn+,Rm MOV @R10+,R11 M(R10) → R11
R10 + 2→ R10
Immediate ✓ MOV #X,TONI MOV #45,TONI #45 → M(TONI)
(1) S = source D = destination

6.3 Operating Modes

The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

  • Active mode (AM)
    • All clocks are active
  • Low-power mode 0 (LPM0)
    • CPU is disabled
    • ACLK and SMCLK remain active. MCLK is disabled
    • FLL+ loop control remains active
  • Low-power mode 1 (LPM1)
    • CPU is disabled
    • FLL+ loop control is disabled
    • ACLK and SMCLK remain active. MCLK is disabled
  • Low-power mode 2 (LPM2)
    • CPU is disabled
    • MCLK, FLL+ loop control and DCOCLK are disabled
    • DCO's dc-generator remains enabled
    • ACLK remains active
  • Low-power mode 3 (LPM3)
    • CPU is disabled
    • MCLK, FLL+ loop control, and DCOCLK are disabled
    • DCO's dc-generator is disabled
    • ACLK remains active
  • Low-power mode 4 (LPM4)
    • CPU is disabled
    • ACLK is disabled
    • MCLK, FLL+ loop control, and DCOCLK are disabled
    • DCO's dc-generator is disabled
    • Crystal oscillator is stopped

6.4 Interrupt Vector Addresses

The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FFC0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 6-3 Interrupt Sources, Flags, and Vectors of MSP430FG43x Configurations

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
Power-Up
External Reset
Watchdog
Flash Memory 		WDTIFG
KEYV (1)		 Reset 0FFFEh 15, highest
NMI
Oscillator Fault
Flash Memory Access Violation 		NMIIFG (1)
OFIFG(1)
ACCVIFG(1)		 (Non)maskable(3)
(Non)maskable
(Non)maskable 		0FFFCh 14
Timer_B3 TBCCR0 CCIFG0(2) Maskable 0FFFAh 13
Timer_B3 TBCCR1 CCIFG1 and TBCCR2 CCIFG2, TBIFG(1)(2) Maskable 0FFF8h 12
Comparator_A CAIFG Maskable 0FFF6h 11
Watchdog Timer WDTIFG Maskable 0FFF4h 10
USART0 Receive URXIFG0 Maskable 0FFF2h 9
USART0 Transmit UTXIFG0 Maskable 0FFF0h 8
ADC12 ADC12IFG (1)(2) Maskable 0FFEEh 7
Timer_A3 TACCR0 CCIFG0(2) Maskable 0FFECh 6
Timer_A3 TACCR1 CCIFG1 and TACCR2 CCIFG2, TAIFG(1)(2) Maskable 0FFEAh 5
I/O Port P1 (Eight Flags) P1IFG.0 to P1IFG.7(1)(2) Maskable 0FFE8h 4
DAC12 DMA DAC12.0IFG, DAC12.1IFG, DMA0IFG(1)(2) Maskable 0FFE6h 3
0FFE4h 2
I/O Port P2 (Eight Flags) P2IFG.0 to P2IFG.7 (1)(2) Maskable 0FFE2h 1
Basic Timer1 BTIFG Maskable 0FFE0h 0, lowest
(1) Multiple source flags
(2) Interrupt flags are located in the module.
(3) (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.

6.5 Special Function Registers (SFRs)

The MSP430 SFRs are located in the lowest address space and are organized as byte-mode registers. SFRs should be accessed with byte instructions.

Legend
rw Bit can be read and written.
rw-0, rw-1 Bit can be read and written. It is Reset or Set by PUC.
rw-(0), rw-1 Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device.

6.5.1 Interrupt Enable Registers 1 and 2

Figure 6-1 Interrupt Enable Register 1 (Address = 0h)
7 6 5 4 3 2 1 0
UTXIE0 URXIE0 ACCVIE NMIIE OFIE WDTIE
rw–0 rw–0 rw–0 rw–0 rw–0 rw–0

Table 6-4 Interrupt Enable Register 1 Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 UTXIE0 RW 0h USART0: UART and SPI transmit-interrupt enable
6 URXIE0 RW 0h USART0: UART and SPI receive-interrupt enable
5 ACCVIE RW 0h Flash access violation interrupt enable
4 NMIIE RW 0h Nonmaskable-interrupt enable
1 OFIE RW 0h Oscillator-fault-interrupt enable
0 WDTIE RW 0h Watchdog-timer interrupt enable. Inactive if watchdog mode is selected.
Active if watchdog timer is configured as a general-purpose timer.
Figure 6-2 Interrupt Enable Register 2 (Address = 1h)
7 6 5 4 3 2 1 0
BTIE
rw–0

Table 6-5 Interrupt Enable Register 2 Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 BTIE RW 0h Basic timer interrupt enable

6.5.2 Interrupt Flag Registers 1 and 2

Figure 6-3 Interrupt Flag Register 1 (Address = 2h)
7 6 5 4 3 2 1 0
UTXIFG0 URXIFG0 NMIIFG OFIFG WDTIFG
rw–1 rw–0 rw–0 rw–1 rw–(0)

Table 6-6 Interrupt Flag Register 1 Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 UTXIFG0 RW 1h USART0: UART and SPI transmit flag
6 URXIFG0 RW 0h USART0: UART and SPI receive flag
4 NMIIFG RW 0h Set by RST/NMI pin
1 OFIFG RW 1h Flag set on oscillator fault
0 WDTIFG RW 0h Set on watchdog timer overflow (in watchdog mode) or security key violation
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode
Figure 6-4 Interrupt Flag Register 2 (Address = 3h)
7 6 5 4 3 2 1 0
BTIFG
rw–0

Table 6-7 Interrupt Flag Register 2 Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 BTIFG RW 0h Basic timer flag

6.5.3 Module Enable Registers 1 and 2

Figure 6-5 Module Enable Register 1 (Address = 4h)
7 6 5 4 3 2 1 0
UTXE0 URXE0
USPIE0
rw–0 rw–0

Table 6-8 Module Enable Register 1 Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
7 UTXE0 RW 0h USART0: UART mode transmit enable
6 URXE0 RW 0h USART0: UART mode receive enable
USPIE0 RW 0h USART0: SPI mode transmit and receive enable
Figure 6-6 Module Enable Register 2 (Address = 5h)
7 6 5 4 3 2 1 0
 
 

6.6 Memory Organization

Table 6-9 shows the memory organization for all device variants.

Table 6-9 Memory Organization

MSP430FG437 MSP430FG438 MSP430FG439
Memory Size 32KB 48KB 60KB
Main: interrupt vector Flash 0FFFFh-0FFE0h 0FFFFh-0FFE0h 0FFFFh-0FFE0h
Main: code memory Flash 0FFFFh-08000h 0FFFFh-04000h 0FFFFh-01100h
Information memory Size 256 Byte 256 Byte 256 Byte
Flash 010FFh-01000h 010FFh-01000h 010FFh-01000h
Boot memory Size 1KB 1KB 1KB
ROM 0FFFh-0C00h 0FFFh-0C00h 0FFFh-0C00h
RAM Size 1KB 2KB 2KB
05FFh-0200h 09FFh-0200h 09FFh-0200h
Peripherals 16-bit 01FFh-0100h 01FFh-0100h 01FFh-0100h
8-bit 0FFh-010h 0FFh-010h 0FFh-010h
8-bit SFR 0Fh-00h 0Fh-00h 0Fh-00h

6.7 Bootstrap Loader (BSL)

The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see MSP430 Programming Via the Bootstrap Loader (BSL) (SLAU319).

BSL FUNCTION PN PACKAGE PINS ZCA PACKAGE PINS
Data Transmit 67 – P1.0 D8 – P1.0
Data Receiver 66 – P1.1 D9 – P1.1

6.8 Flash Memory

The flash memory can be programmed via the JTAG port, the bootstrap loader, or in system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

  • Flash memory has n segments of main memory and two segments of information memory (A and B) of 128 bytes each. Each segment in main memory is 512 bytes in size.
  • Segments 0 to n may be erased in one step, or each segment may be individually erased.
  • Segments A and B can be erased individually, or as a group with segments 0 to n. Segments A and B are also called information memory.
  • New devices may have some bytes programmed in the information memory (needed for test during manufacturing). The user should perform an erase of the information memory prior to the first use.
flash_memory_segments_slas380.gif
A. MSP430FG43x flash segment n = 256 bytes.
Figure 6-7 Flash Memory Segments

6.9 Peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x4xx Family User's Guide (SLAU056).

6.9.1 DMA Controller

The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to or from a peripheral.

6.9.2 Oscillator and System Clock

The clock system in the MSP430FG43x family of devices is supported by the FLL+ module, which includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO), and a high frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and low power consumption. The FLL+ features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 µs. The FLL+ module provides the following clock signals:

  • Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal
  • Main clock (MCLK), the system clock used by the CPU
  • Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules
  • ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8

6.9.3 Brownout, Supply Voltage Supervisor

The brownout circuit is implemented to provide the proper internal reset signal to the device during power-on and power-off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not automatically reset).

The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not have ramped to VCC(min) at that time. The user must make sure that the default FLL+ settings are not changed until VCC reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).

6.9.4 Digital I/O

There are six 8-bit I/O ports implemented—ports P1 through P6:

  • All individual I/O bits are independently programmable.
  • Any combination of input, output, and interrupt conditions is possible.
  • Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
  • Read and write access to port-control registers is supported by all instructions

6.9.5 Basic Timer1

The Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. The Basic Timer1 can be used to generate periodic interrupts and clock for the LCD module.

6.9.6 LCD Drive

The LCD driver generates the segment and common signals required to drive an LCD display. The LCD controller has dedicated data memory to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.

6.9.7 OA

The MSP430FG43x has three configurable low-current general-purpose operational amplifiers. Each OA input and output terminal is software-selectable and offers a flexible choice of connections for various applications. The OA op amps primarily support front-end analog signal conditioning prior to analog-to-digital conversion.

6.9.8 Watchdog Timer (WDT)

The primary function of the WDT module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.

6.9.9 USART0

The MSP430FG43x has one hardware universal synchronous/asynchronous receive transmit (USART) peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels.

6.9.10 Timer_A3

Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 6-10 Timer_A3 Signal Connections

INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK MODULE OUTPUT SIGNAL OUTPUT PIN NUMBER
ZCA PN PN ZCA
B10 - P1.5 62 - P1.5 TACLK TACLK
ACLK ACLK
SMCLK SMCLK Timer NA
B10 - P1.5 62 - P1.5 TACLK INCLK
D8 - P1.0 67 - P1.0 TA0 CCI0A 67 - P1.0 D8 - P1.0
D9 - P1.1 66 - P1.1 TA0 CCI0B
DVSS GND CCR0 TA0
DVCC VCC
B9 - P1.2 65 - P1.2 TA1 CCI1A 65 - P1.2 B9 - P1.2
CAOUT (internal) CCI1B ADC12 (internal)
DVSS GND CCR1 TA1
DVCC VCC
C11 - P2.0 59 - P2.0 TA2 CCI2A 59 - P2.0 C11 - P2.0
ACLK (internal) CCI2B
DVSS GND CCR2 TA2
DVCC VCC

6.9.11 Timer_B3

Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 6-11 Timer_B3 Signal Connections

INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK MODULE OUTPUT SIGNAL OUTPUT PIN NUMBER
ZCA PN PN ZCA
E9 - P1.4 63 - P1.4 TBCLK TBCLK
ACLK ACLK
SMCLK SMCLK Timer NA
E9 - P1.4 63 - P1.4 TBCLK INCLK
D11 - P2.1 58 - P2.1 TB0 CCI0A 58 - P2.1 D11 - P2.1
D11 - P2.1 58 - P2.1 TB0 CCI0B ADC12 (internal)
DVSS GND CCR0 TB0
DVCC VCC
E11 - P2.2 57 - P2.2 TB1 CCI1A 57 - P2.2 E11 - P2.2
E11 - P2.2 57 - P2.2 TB1 CCI1B ADC12 (internal)
DVSS GND CCR1 TB1
DVCC VCC
F11 - P2.3 56 - P2.3 TB2 CCI2A 56 - P2.3 F11 - P2.3
F11 - P2.3 56 - P2.3 TB2 CCI2B
DVSS GND CCR2 TB2
DVCC VCC

6.9.12 Comparator_A

The primary function of the comparator_A module is to support precision slope analog-to-digital conversions, battery-voltage supervision, and monitoring of external analog signals.

6.9.13 ADC12

The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator and a 16 word conversion-and-control buffer. The conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention.

6.9.14 DAC12

The DAC12 module is a 12-bit, R-ladder, voltage output DAC. The DAC12 may be used in 8- or 12-bit mode, and may be used in conjunction with the DMA controller. When multiple DAC12 modules are present, they may be grouped together for synchronous operation.

6.9.15 Peripheral File Map

Table 6-12 shows peripherals with word-access registers, and Table 6-13 shows peripherals with byte-access registers.

Table 6-12 Peripherals With Word Access

PERIPHERAL REGISTER NAME ACRONYM OFFSET
Watchdog Watchdog timer control WDTCTL 0120h
Timer_B3 Capture/compare register 2 TBCCR2 0196h
Capture/compare register 1 TBCCR1 0194h
Capture/compare register 0 TBCCR0 0192h
Timer_B register TBR 0190h
Capture/compare control 2 TBCCTL2 0186h
Capture/compare control 1 TBCCTL1 0184h
Capture/compare control 0 TBCCTL0 0182h
Timer_B control TBCTL 0180h
Timer_B interrupt vector TBIV 011Eh
Capture/compare register 2 TACCR2 0176h
Capture/compare register 1 TACCR1 0174h
Capture/compare register 0 TACCR0 0172h
Timer_A3 Timer_A register TAR 0170h
Capture/compare control 2 TACCTL2 0166h
Capture/compare control 1 TACCTL1 0164h
Capture/compare control 0 TACCTL0 0162h
Timer_A control TACTL 0160h
Timer_A interrupt vector TAIV 012Eh
Flash Flash control 3 FCTL3 012Ch
Flash control 2 FCTL2 012Ah
Flash control 1 FCTL1 0128h
DMA DMA module control 0 DMACTL0 0122h
DMA module control 1 DMACTL1 0124h
DMA channel 0 control DMA0CTL 01E0h
DMA channel 0 source address DMA0SA 01E2h
DMA channel 0 destination address DMA0DA 01E4h
DMA channel 0 transfer size DMA0SZ 01E6h
ADC12
(See also Table 6-13)		 Conversion memory 15 ADC12MEM15 015Eh
Conversion memory 14 ADC12MEM14 015Ch
Conversion memory 13 ADC12MEM13 015Ah
Conversion memory 12 ADC12MEM12 0158h
Conversion memory 11 ADC12MEM11 0156h
Conversion memory 10 ADC12MEM10 0154h
Conversion memory 9 ADC12MEM9 0152h
Conversion memory 8 ADC12MEM8 0150h
Conversion memory 7 ADC12MEM7 014Eh
Conversion memory 6 ADC12MEM6 014Ch
Conversion memory 5 ADC12MEM5 014Ah
Conversion memory 4 ADC12MEM4 0148h
Conversion memory 3 ADC12MEM3 0146h
Conversion memory 2 ADC12MEM2 0144h
Conversion memory 1 ADC12MEM1 0142h
Conversion memory 0 ADC12MEM0 0140h
Interrupt-vector-word register ADC12IV 01A8h
Interrupt-enable register ADC12IE 01A6h
Interrupt-flag register ADC12IFG 01A4h
Control register 1 ADC12CTL1 01A2h
Control register 0 ADC12CTL0 01A0h
DAC12 DAC12_1 data DAC12_1DAT 01CAh
DAC12_1 control DAC12_1CTL 01C2h
DAC12_0 data DAC12_0DAT 01C8h
DAC12_0 control DAC12_0CTL 01C0h

Table 6-13 Peripherals With Byte Access

PERIPHERAL REGISTER NAME ACRONYM OFFSET
OA2 Operational Amplifier 2 control register 1 OA2CTL1 0C5h
Operational Amplifier 2 control register 0 OA2CTL0 0C4h
OA1 Operational Amplifier 1 control register 1 OA1CTL1 0C3h
Operational Amplifier 1 control register 0 OA1CTL0 0C2h
OA0 Operational Amplifier 0 control register 1 OA0CTL1 0C1h
Operational Amplifier 0 control register 0 OA0CTL0 0C0h
LCD LCD memory 20 LCDM20 0A4h
  ⋮   ⋮   ⋮
LCD memory 16 LCDM16 0A0h
LCD memory 15 LCDM15 09Fh
  ⋮   ⋮   ⋮
LCD memory 1 LCDM1 091h
LCD control and mode LCDCTL 090h
ADC12
(Memory control registers require byte access)		 ADC memory-control register 15 ADC12MCTL15 08Fh
ADC memory-control register 14 ADC12MCTL14 08Eh
ADC memory-control register 13 ADC12MCTL13 08Dh
ADC memory-control register 12 ADC12MCTL12 08Ch
ADC memory-control register 11 ADC12MCTL11 08Bh
ADC memory-control register 10 ADC12MCTL10 08Ah
ADC memory-control register 9 ADC12MCTL9 089h
ADC memory-control register 8 ADC12MCTL8 088h
ADC memory-control register 7 ADC12MCTL7 087h
ADC memory-control register 6 ADC12MCTL6 086h
ADC memory-control register 5 ADC12MCTL5 085h
ADC memory-control register 4 ADC12MCTL4 084h
ADC memory-control register 3 ADC12MCTL3 083h
ADC memory-control register 2 ADC12MCTL2 082h
ADC memory-control register 1 ADC12MCTL1 081h
ADC memory-control register 0 ADC12MCTL0 080h
USART0
(UART or SPI mode) 		Transmit buffer U0TXBUF 077h
Receive buffer U0RXBUF 076h
Baud rate U0BR1 075h
Baud rate U0BR0 074h
Modulation control U0MCTL 073h
Receive control U0RCTL 072h
Transmit control U0TCTL 071h
USART control U0CTL 070h
Comparator_A Comparator_A port disable CAPD 05Bh
Comparator_A control 2 CACTL2 05Ah
Comparator_A control 1 CACTL1 059h
BrownOUT, SVS SVS control register (Reset by brownout signal) SVSCTL 056h
FLL+ Clock FLL+ Control 1 FLL_CTL1 054h
FLL+ Control 0 FLL_CTL0 053h
System clock frequency control SCFQCTL 052h
System clock frequency integrator SCFI1 051h
System clock frequency integrator SCFI0 050h
Basic Timer1 BT counter 2 BTCNT2 047h
BT counter 1 BTCNT1 046h
BT control BTCTL 040h
Port P6 Port P6 selection P6SEL 037h
Port P6 direction P6DIR 036h
Port P6 output P6OUT 035h
Port P6 input P6IN 034h
Port P5 Port P5 selection P5SEL 033h
Port P5 direction P5DIR 032h
Port P5 output P5OUT 031h
Port P5 input P5IN 030h
Port P4 Port P4 selection P4SEL 01Fh
Port P4 direction P4DIR 01Eh
Port P4 output P4OUT 01Dh
Port P4 input P4IN 01Ch
Port P3 Port P3 selection P3SEL 01Bh
Port P3 direction P3DIR 01Ah
Port P3 output P3OUT 019h
Port P3 input P3IN 018h
Port P2 Port P2 selection P2SEL 02Eh
Port P2 interrupt enable P2IE 02Dh
Port P2 interrupt-edge select P2IES 02Ch
Port P2 interrupt flag P2IFG 02Bh
Port P2 direction P2DIR 02Ah
Port P2 output P2OUT 029h
Port P2 input P2IN 028h
Port P1 Port P1 selection P1SEL 026h
Port P1 interrupt enable P1IE 025h
Port P1 interrupt-edge select P1IES 024h
Port P1 interrupt flag P1IFG 023h
Port P1 direction P1DIR 022h
Port P1 output P1OUT 021h
Port P1 input P1IN 020h
Special functions SFR module enable 2 ME2 005h
SFR module enable 1 ME1 004h
SFR interrupt flag 2 IFG2 003h
SFR interrupt flag 1 IFG1 002h
SFR interrupt enable 2 IE2 001h
SFR interrupt enable 1 IE1 000h

6.10 Input/Output Schematics

6.10.1 Port P1, P1.0 to P1.5, Input/Output With Schmitt Trigger

port_p1_012345_slas380.gif
PnSEL.x PnDIR.x Direction Control From Module PnOUT.x Module X OUT PnIN.x Module X IN PnIE.x PnIFG.x PnIES.x
P1SEL.0 P1DIR.0 P1DIR.0 P1OUT0 Out0 sig.(1) P1IN.0 CCI0A(1) P1IE.0 P1IFG.0 P1IES.0
P1SEL.1 P1DIR.1 P1DIR.1 P1OUT.1 MCLK P1IN.1 CCI0B(1) P1IE.1 P1IFG.1 P1IES.1
P1SEL.2 P1DIR.2 P1DIR.2 P1OUT.2 Out1 sig.(1) P1IN.2 CCI1A(1) P1IE.2 P1IFG.2 P1IES.2
P1SEL.3 P1DIR.3 P1DIR.3 P1OUT.3 SVSOUT P1IN.3 TBOUTH(2) P1IE.3 P1IFG.3 P1IES.3
P1SEL.4 P1DIR.4 P1DIR.4 P1OUT.4 SMCLK P1IN.4 TBCLK(2) P1IE.4 P1IFG.4 P1IES.4
P1SEL.5 P1DIR.5 P1DIR5 P1OUT.5 ACLK P1IN.5 TACLK(1) P1IE.5 P1IFG.5 P1IES.5
(1) Timer_A
(2) Timer_B

6.10.2 Port P1, P1.6 and P1.7, Input/Output With Schmitt Trigger

port_p1_67_slas380.gif

6.10.3 Port P2, P2.0 and P2.4 to P2.5, Input/Output With Schmitt Trigger

port_p2_045_slas380.gif
PnSel.x PnDIR.x Direction Control From Module PnOUT.x Module X OUT PnIN.x Module X IN PnIE.x PnIFG.x PnIES.x
P2Sel.0 P2DIR.0 P2DIR.0 P2OUT.0 Out2 sig.(1) P2IN.0 CCI2A(1) P2IE.0 P2IFG.0 P2IES.0
P2Sel.4 P2DIR.4 DVCC P2OUT.4 UTXD0(2) P2IN.4 unused P2IE.4 P2IFG.4 P2IES.4
P2Sel.5 P2DIR.5 DVSS P2OUT.5 DVSS P2IN.5 URXD0(2) P2IE.5 P2IFG.5 P2IES.5
(1) Timer_A
(2) USART0

6.10.4 Port P2, P2.1 to P2.3, Input/Output With Schmitt Trigger

port_p2_123_slas380.gif
PnSel.x PnDIR.x Direction Control From Module PnOUT.x Module X OUT PnIN.x Module X IN PnIE.x PnIFG.x PnIES.x
P2Sel.1 P2DIR.1 P2DIR.1 P2OUT.1 Out0 sig.(1) P2IN.1 CCI0A(1)
CCI0B		 P2IE.1 P2IFG.1 P2IES.1
P2Sel.2 P2DIR.2 P2DIR.2 P2OUT.2 Out1 sig.(1) P2IN.2 CCI1A(1)
CCI1B		 P2IE.2 P2IFG.2 P2IES.2
P2Sel.3 P2DIR.3 P2DIR.3 P2OUT.3 Out2 sig.(1) P2IN.3 CCI2A(1)
CCI2B		 P2IE.3 P2IFG.3 P2IES.3
(1) Timer_B

6.10.5 Port P2, P2.6 and P2.7, Input/Output With Schmitt Trigger

port_p2_67_slas380.gif
PnSel.x PnDIR.x Direction Control From Module PnOUT.x Module X OUT PnIN.x Module X IN PnIE.x PnIFG.x PnIES.x Port/LCD
P2Sel.6 P2DIR.6 P2DIR.6 P2OUT.6 CAOUT(1) P2IN.6 unused P2IE.6 P2IFG.6 P2IES.6 0: LCDPx < 02h
P2Sel.7 P2DIR.7 P2DIR.7 P2OUT.7 ADC12CLK (2) P2IN.7 unused P2IE.7 P2IFG.7 P2IES.7 0: LCDPx < 02h
(1) Comparator_A
(2) ADC12

6.10.6 Port P3, P3.0 to P3.3, Input/Output With Schmitt Trigger

port_p3_0123_slas380.gif
PnSel.x PnDIR.x Direction Control From Module PnOUT.x Module X OUT PnIN.x Module X IN
P3Sel.0 P3DIR.0 DVSS P3OUT.0 DVSS P3IN.0 STE0(in)
P3Sel.1 P3DIR.1 DCM_SIMO0 P3OUT.1 SIMO0(out) P3IN.1 SIMO0(in)
P3Sel.2 P3DIR.2 DCM_SOMI0 P3OUT.2 SOMIO(out) P3IN.2 SOMI0(in)
P3Sel.3 P3DIR.3 DCM_UCLK0 P3OUT.3 UCLK0(out) P3IN.3 UCLK0(in)
port_p3_0123_direction_slas380.gif

6.10.7 Port P3, P3.4 to P3.7, Input/Output With Schmitt Trigger

port_p3_4567_slas380.gif
PnSel.x PnDIR.x Direction Control From Module PnOUT.x Module X OUT PnIN.x Module X IN
P3SEL.4 P3DIR.4 P3DIR.4 P3OUT.4 DVSS P3IN.4 unused
P3SEL.5 P3DIR.5 P3DIR.5 P3OUT.5 DVSS P3IN.5 unused
P3SEL.6 P3DIR.6 P3DIR.6 P3OUT.6 DVSS P3IN.6 DMAE0
P3SEL.7 P3DIR.7 P3DIR.7 P3OUT.7 DVSS P3IN.7 unused

6.10.8 Port P4, P4.0 to P4.5, Input/Output With Schmitt Trigger

port_p4_012345_slas380.gif
PnSEL.x PnDIR.x Direction Control From Module PnOUT.x Module X OUT PnIN.x Module X IN
P4SEL.0 P4DIR.0 P4DIR.0 P4OUT.0 DVSS P4IN.0 unused
P4SEL.1 P4DIR.1 P4DIR.1 P4OUT.1 DVSS P4IN.1 unused
P4SEL.2 P4DIR.2 P4DIR.2 P4OUT.2 DVSS P4IN.2 unused
P4SEL.3 P4DIR.3 P4DIR.3 P4OUT.3 DVSS P4IN.3 unused
P4SEL.4 P4DIR.4 P4DIR.4 P4OUT.4 DVSS P4IN.4 unused
P4SEL.5 P4DIR.5 P4DIR.5 P4OUT.5 DVSS P4IN.5 unused
DEVICE PORT BITS PORT FUNCTION LCD SEGMENT FUNCTION
MSP430FG43x P4.0 to P4.5 LCDPx < 01h LCDPx ≥ 01h

6.10.9 Port P4, P4.6, Input/Output With Schmitt Trigger

port_p4_6_slas380.gif
PnSEL.x PnDIR.x Direction Control From Module PnOUT.x Module X OUT PnIN.x Module X IN
P4SEL.6 P4DIR.6 P4DIR.6 P4OUT.6 DVSS P4IN.6 unused
DEVICE PORT BITS PORT FUNCTION LCD SEGMENT FUNCTION
MSP430FG43x P4.6 LCDPx < 01h LCDPx ≥ 01h

6.10.10 Port P4, P4.7, Input/Output With Schmitt Trigger

port_p4_7_slas380.gif
PnSel.x PnDIR.x Direction Control From Module PnOUT.x Module X OUT PnIN.x Module X IN
P4Sel.7 P4DIR.7 P4DIR.7 P4OUT.7 DVSS P4IN.7 Unused
DEVICE PORT BITS PORT FUNCTION LCD SEGMENT FUNCTION
MSP430FG43x P4.7 LCDPx < 01h LCDPx ≥ 01h

6.10.11 Port P5, P5.0, Input/Output With Schmitt Trigger

port_p5_0_slas380.gif
PnSEL.x PnDIR.x Direction Control From Module PnOUT.x Module X OUT PnIN.x Module X IN
P5SEL.0 P5DIR.0 P5DIR.0 P5OUT.0 DVSS P5IN.0 unused
DEVICE PORT BITS PORT FUNCTION LCD SEGMENT FUNCTION
MSP430FG43x P5.0 LCDPx < 01h LCDPx ≥ 01h

6.10.12 Port P5, P5.1, Input/Output With Schmitt Trigger

port_p5_1_slas380.gif
Function Description P5SEL.1 LCDPx DAC12.1OPS DAC12.1AMPx
DAC12 3-State X X 1 0
0 V X X 1 1
DAC1 output
(the output voltage can be converted with ADC12, channel A12)		 X X 1 > 1
ADC12 Channel 12, A12 1 X 0 X
LCD Segment S0, initial state 0 ≥ 01h 0 X
Port P5.1 0 < 01h 0 X
PnSEL.x PnDIR.x Direction Control From Module PnOUT.x Module X OUT PnIN.x Module X IN Segment Port/LCD
P5SEL.1 P5DIR.1 P5DIR.1 P5OUT.1 DVSS P5IN.1 Unused S0 0: LCDPx < 01h

6.10.13 Port P5, P5.2 to P5.4, Input/Output With Schmitt Trigger

port_p5_234_slas380.gif
PnSel.x PnDIR.x Direction Control From Module PnOUT.x Module X OUT PnIN.x Module X IN LCD signal Port/LCD
P5Sel.2 P5DIR.2 P5DIR.2 P5OUT.2 DVSS P5IN.2 Unused COM1 P5SEL.2
P5Sel.3 P5DIR.3 P5DIR.3 P5OUT.3 DVSS P5IN.3 Unused COM2 P5SEL.3
P5Sel.4 P5DIR.4 P5DIR.4 P5OUT.4 DVSS P5IN.4 Unused COM3 P5SEL.4

6.10.14 Port P5, P5.5 to P5.7, Input/Output With Schmitt Trigger

port_p5_567_slas380.gif
PnSel.x PnDIR.x Direction Control From Module PnOUT.x Module X OUT PnIN.x Module X IN LCD signal Port/LCD
P5Sel.5 P5DIR.5 P5DIR.5 P5OUT.5 DVSS P5IN.5 Unused R13 P5SEL.5
P5Sel.6 P5DIR.6 P5DIR.6 P5OUT.6 DVSS P5IN.6 Unused R23 P5SEL.6
P5Sel.7 P5DIR.7 P5DIR.7 P5OUT.7 DVSS P5IN.7 Unused R33 P5SEL.7

6.10.15 Port P6, P6.0, P6.2, and P6.4, Input/Output With Schmitt Trigger

port_p6_024_slas380.gif
PnSel.x(1) PnDIR.x Direction Control From Module PnOUT.x Module X OUT PnIN.x Module X IN
P6Sel.0 P6DIR.0 P6DIR.0 P6OUT.0 DVSS P6IN.0 unused
P6Sel.2 P6DIR.2 P6DIR.2 P6OUT.2 DVSS P6IN.2 unused
P6Sel.4 P6DIR.4 P6DIR.4 P6OUT.4 DVSS P6IN.4 unused
(1) The signal at pin P6.x/Ax is used by the 12-bit ADC module.

6.10.16 Port P6, P6.1, Input/Output With Schmitt Trigger

port_p6_1_slas380.gif
PnSel.x(1) PnDIR.x Direction Control From Module PnOUT.x Module X OUT PnIN.x Module X IN
P6Sel.1 P6DIR.1 P6DIR.1 P6OUT.1 DVSS P6IN.1 unused
(1) The signal at pin P6.x/Ax is used by the 12-bit ADC module.

6.10.17 Port P6, P6.3, Input/Output With Schmitt Trigger

port_p6_3_slas380.gif
PnSel.x(1) PnDIR.x Direction Control From Module PnOUT.x Module X OUT PnIN.x Module X IN
P6Sel.3 P6DIR.3 P6DIR.3 P6OUT.3 DVSS P6IN.3 unused
(1) The signal at pin P6.x/Ax is used by the 12-bit ADC module.

6.10.18 Port P6, P6.5, Input/Output With Schmitt Trigger

port_p6_5_slas380.gif
PnSel.x(1) PnDIR.x Direction Control From Module PnOUT.x Module X OUT PnIN.x Module X IN
P6Sel.5 P6DIR.5 P6DIR.5 P6OUT.5 DVSS P6IN.5 unused
(1) The signal at pins P6.x/Ax is used by the 12-bit ADC module.

6.10.19 Port P6, P6.6, Input/Output With Schmitt Trigger

port_p6_6_slas380.gif
PnSel.x(1) PnDIR.x Direction Control From Module PnOUT.x Module X OUT PnIN.x Module X IN
P6Sel.6 P6DIR.6 P6DIR.6 P6OUT.6 DVSS P6IN.6 unused
(1) The signal at pins P6.x/Ax is used by the 12-bit ADC module.

6.10.20 Port P6, P6.7, Input/Output With Schmitt Trigger

port_p6_7_slas380.gif
PnSel.x(1) PnDIR.x Direction Control From Module PnOUT.x Module X OUT PnIN.x Module X IN
P6Sel.7 P6DIR.7 P6DIR.7 P6OUT.7 DVSS P6IN.7 unused
(1) The signal at pins P6.x/Ax is used by the 12-bit ADC module. The signal at pin P6.7/A7/SVSIN is also connected to the input multiplexer in the module brownout/supply voltage supervisor.

6.10.21 VeREF+/DAC0

port_veref_dac_slas380.gif

6.10.22 JTAG Pins TMS, TCK, TDI/TCLK, TDO/TDI, Input/Output With Schmitt Trigger or Output

port_jtag_slas380.gif

6.10.23 JTAG Fuse Check Mode

MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current (I(TF)) of 1 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption.

Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse check mode has the potential to be activated.

The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see Figure 6-8). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition). The JTAG pins are terminated internally and therefore do not require external termination.

fuse_check_current_slas380.gifFigure 6-8 Fuse Check Mode Current