SLAS380D April 2004 – November 2014 MSP430FG437 , MSP430FG438 , MSP430FG439
PRODUCTION DATA.
MIN | MAX | UNIT | |
---|---|---|---|
Voltage applied at VCC to VSS | –0.3 | 4.1 | V |
Voltage applied to any pin(2) | –0.3 | VCC + 0.3 | V |
Diode current at any device terminal | ±2 | mA |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Tstg | Storage temperature range | Unprogrammed device | -55 | 150 | °C |
Programmed device | -40 | 85 |
MIN | NOM | MAX | UNIT | |||||
---|---|---|---|---|---|---|---|---|
VCC | Supply voltage(1)
(AVCC = DVCC1 = DVCC2 = VCC) |
During program execution | 1.8 | 3.6 | V | |||
During program execution, SVS enabled and PORON = 1(2) |
2 | 3.6 | ||||||
During flash memory programming | 2.7 | 3.6 | ||||||
VSS | Supply voltage(1)
(AVSS = DVSS1 = DVSS2 = VSS) |
0 | 0 | V | ||||
TA | Operating free-air temperature range | –40 | 85 | °C | ||||
f(LFXT1) | XT1 crystal frequency(3) | LF selected, XTS_FLL = 0 | Watch crystal | 32.768 | kHz | |||
XT1 selected, XTS_FLL = 1 | Ceramic resonator | 450 | 8000 | |||||
XT1 selected, XTS_FLL = 1 | Crystal | 1000 | 8000 | |||||
f(XT2) | XT2 crystal frequency | Ceramic resonator | 450 | 8000 | kHz | |||
Crystal | 1000 | 8000 | ||||||
f(System) | Processor frequency (signal MCLK) | VCC = 1.8 V | dc | 4.15 | MHz | |||
VCC = 3.6 V | dc | 8 |
PARAMETER | TA | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
I(AM) | Active mode(1)
f(MCLK) = f(SMCLK) = 1 MHz, f(ACLK) = 32768 Hz, XTS_FLL = 0, SELM = (0,1) |
–40°C to 85°C | 2.2 V | 300 | 370 | µA | |
3 V | 470 | 570 | |||||
I(LPM0) | Low-power mode (LPM0)(1)(4) | –40°C to 85°C | 2.2 V | 55 | 70 | µA | |
3 V | 95 | 110 | |||||
I(LPM2) | Low-power mode (LPM2), f(MCLK) = f(SMCLK) = 0 MHz, f(ACLK) = 32768 Hz, SCG0 = 0(2)(4) |
–40°C to 85°C | 2.2 V | 11 | 14 | µA | |
3 V | 17 | 22 | |||||
I(LPM3) | Low-power mode (LPM3) f(MCLK) = f(SMCLK) = 0 MHz, f(ACLK) = 32768 Hz, SCG0 = 1(2)(3)(4) |
–40°C | 2.2 V | 1 | 2 | µA | |
25°C | 1.1 | 2 | |||||
60°C | 2 | 3 | |||||
85°C | 3.5 | 6 | |||||
–40°C | 3 V | 1.8 | 2.8 | ||||
25°C | 1.6 | 2.7 | |||||
60°C | 2.5 | 3.5 | |||||
85°C | 4.2 | 7.5 | |||||
I(LPM4) | Low-power mode (LPM4) f(MCLK) = f(SMCLK) = 0 MHz, f(ACLK) = 0 Hz, SCG0 = 1(2)(4) |
–40°C | 2.2 V | 0.1 | 0.5 | µA | |
25°C | 0.1 | 0.5 | |||||
60°C | 0.7 | 1.1 | |||||
85°C | 1.7 | 3 | |||||
–40°C | 3 V | 0.1 | 0.8 | ||||
25°C | 0.1 | 0.8 | |||||
60°C | 0.8 | 1.2 | |||||
85°C | 1.9 | 3.5 |
Current consumption of active mode versus system frequency:
I(AM) = I(AM) [1 MHz] × f(System) [MHz]
Current consumption of active mode versus supply voltage:
I(AM) = I(AM) [3 V] + 175 µA/V × (VCC – 3 V)
PARAMETER | VCC | MIN | MAX | UNIT | |
---|---|---|---|---|---|
VIT+ | Positive-going input threshold voltage | 2.2 V | 1.1 | 1.55 | V |
3 V | 1.5 | 1.98 | |||
VIT– | Negative-going input threshold voltage | 2.2 V | 0.4 | 0.9 | V |
3 V | 0.9 | 1.3 | |||
Vhys | Input voltage hysteresis (VIT+ – VIT– ) | 2.2 V | 0.3 | 1.1 | V |
3 V | 0.5 | 1 |
PARAMETER | TEST CONDITIONS | VCC | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
t(int) | External interrupt timing | Port P1, P2: P1.x to P2.x, external trigger signal for the interrupt flag(1) | 2.2 V | 62 | ns | |
3 V | 50 | |||||
t(cap) | Timer_A or Timer_B capture timing | TA0, TA1, TA2 TB0, TB1, TB2 |
2.2 V | 62 | ns | |
3 V | 50 | |||||
f(TAext) | Timer_A or Timer_B clock frequency externally applied to pin | TACLK, TBCLK, INCLK: t(H) = t(L) | 2.2 V | 8 | MHz | |
f(TBext) | 3 V | 10 | ||||
f(TAint) | Timer_A or Timer_B clock frequency | SMCLK or ACLK signal selected | 2.2 V | 8 | MHz | |
f(TBint) | 3 V | 10 |
PARAMETER | TEST CONDITIONS | MIN | MAX | UNIT | ||
---|---|---|---|---|---|---|
Ilkg(Px.y) | Leakage current, Port Px | V(Px.y)(2) | VCC = 2.2 V, 3 V | ±50 | nA |
PARAMETER | TEST CONDITIONS | MIN | MAX | UNIT | |
---|---|---|---|---|---|
VOH | High-level output voltage | IOH(max) = –1.5 mA, VCC = 2.2 V(1) | VCC – 0.25 | VCC | V |
IOH(max) = –6 mA, VCC = 2.2 V(2) | VCC – 0.6 | VCC | |||
IOH(max) = –1.5 mA, VCC = 3 V(1) | VCC – 0.25 | VCC | |||
IOH(max) = –6 mA, VCC = 3 V(2) | VCC – 0.6 | VCC | |||
VOL | Low-level output voltage | IOL(max) = 1.5 mA, VCC = 2.2 V(1) | VSS | VSS + 0.25 | V |
IOL(max) = 6 mA, VCC = 2.2 V(2) | VSS | VSS + 0.6 | |||
IOL(max) = 1.5 mA, VCC = 3 V(1) | VSS | VSS + 0.25 | |||
IOL(max) = 6 mA, VCC = 3 V(2) | VSS | VSS + 0.6 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
f(Px.y) | (1 ≤ × ≤ 6, 0 ≤ y ≤ 7) | CL = 20 F, IL = ±1.5 mA |
VCC = 2.2 V, 3 V | dc | f(System) | MHz | |
f(MCLK) | P1.1/TA0/MCLK | CL = 20 pF | f(System) | MHz | |||
f(SMCLK) | P1.4/TBCLK/SMCLK | ||||||
f(ACLK) | P1.5/TACLK/ACLK | ||||||
t(Xdc) | Duty cycle of output frequency | P1.5/TACLK/ACLK, CL = 20 pF, VCC = 2.2 V, 3 V |
f(ACLK) = f(LFXT1) = f(XT1) | 40% | 60% | ||
f(ACLK) = f(LFXT1) = f(LF) | 30% | 70% | |||||
f(ACLK) = f(LFXT1) | 50% | ||||||
P1.1/TA0/MCLK, CL = 20 pF, VCC = 2.2 V, 3 V |
f(MCLK) = f(XT1) | 40% | 60% | ||||
f(MCLK) = f(DCOCLK) | 50% – 15 ns |
50% | 50%+ 15 ns |
||||
P1.4/TBCLK/SMCLK, CL = 20 pF, VCC = 2.2 V, 3 V |
f(SMCLK) = f(XT2) | 40% | 60% | ||||
f(SMCLK) = f(DCOCLK) | 50% – 15 ns |
50% | 50%+ 15 ns |
PARAMETER | TEST CONDITIONS | MIN | MAX | UNIT | ||
---|---|---|---|---|---|---|
td(LPM3) | Delay time | f = 1 MHz | VCC = 2.2 V, 3 V | 6 | µs | |
f = 2 MHz | 6 | |||||
f = 3 MHz | 6 |
PARAMETER | TEST CONDITIONS | MIN | MAX | UNIT | ||
---|---|---|---|---|---|---|
VRAMh | CPU halted(1) | 1.6 | V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
V(33) | Analog voltage | Voltage at P5.7/R33 | VCC = 3 V | 2.5 | VCC + 0.2 | V | |
V(23) | Voltage at P5.6/R23 | [V(33)−V(03)] × 2/3 + V(03) | |||||
V(13) | Voltage at P5.5/R13 | [V(33)−V(03)] × 1/3 + V(03) | |||||
V(33)-V(03) | Voltage at R33 to R03 | 2.5 | VCC + 0.2 | ||||
I(R03) | Input leakage | R03 = VSS | No load at all segment and common lines, VCC = 3 V | ±20 | nA | ||
I(R13) | P5.5/R13 = VCC/3 | ±20 | |||||
I(R23) | P5.6/R23 = 2 × VCC/3 | ±20 | |||||
V(Sxx0) | Segment line voltage | I(Sxx) = −3 µA, VCC = 3 V | V(03) | V(03) - 1 | V | ||
V(Sxx1) | V(13) | V(13) - 1 | |||||
V(Sxx2) | V(23) | V(23) - 1 | |||||
V(Sxx3) | V(33) | V(33) - 1 |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
I(CC) | CAON = 1, CARSEL = 0, CAREF = 0 | 2.2 V | 25 | 40 | µA | ||
3 V | 45 | 60 | |||||
I(Refladder/RefDiode) | CAON = 1, CARSEL = 0, CAREF = (1,2,3), No load at P1.6/CA0 and P1.7/CA1 |
2.2 V | 30 | 50 | µA | ||
3 V | 45 | 71 | |||||
V(Ref025) | (Voltage at 0.25 VCC node) / VCC | PCA0 = 1, CARSEL = 1, CAREF = 1, No load at P1.6/CA0 and P1.7/CA1 |
2.2 V, 3 V | 0.23 | 0.24 | 0.25 | |
V(Ref050) | (Voltage at 0.55 VCC node) / VCC | PCA0 = 1, CARSEL = 1, CAREF = 2, No load at P1.6/CA0 and P1.7/CA1 |
2.2 V, 3 V | 0.47 | 0.48 | 0.5 | |
V(RefVT) | See Figure 5-6 and Figure 5-7 | PCA0 = 1, CARSEL = 1, CAREF = 3, No load at P1.6/CA0 and P1.7/CA1, TA = 85°C |
2.2 V | 390 | 480 | 540 | mV |
3 V | 400 | 490 | 550 | ||||
VIC | Common-mode input voltage range | CAON = 1 | 2.2 V, 3 V | 0 | VCC –1 | V | |
Vp – VS | Offset voltage | See (2) | 2.2 V, 3 V | –30 | 30 | mV | |
Vhys | Input hysteresis | CAON = 1 | 2.2 V, 3 V | 0 | 0.7 | 1.4 | mV |
t(response LH) | TA = 25°C, Overdrive 10 mV, without filter: CAF = 0 |
2.2 V | 160 | 210 | 300 | ns | |
3 V | 80 | 150 | 240 | ||||
TA = 25°C, Overdrive 10 mV, with filter: CAF = 1 |
2.2 V | 1.4 | 1.9 | 3.4 | µs | ||
3 V | 0.9 | 1.5 | 2.6 | ||||
t(response HL) | TA = 25°C, Overdrive 10 mV, without filter: CAF = 0 |
2.2 V | 130 | 210 | 300 | ns | |
3 V | 80 | 150 | 240 | ||||
TA = 25°C, Overdrive 10 mV, with filter: CAF = 1 |
2.2 V | 1.4 | 1.9 | 3.4 | µs | ||
3 V | 0.9 | 1.5 | 2.6 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
td(BOR) | Brownout(2) | 2000 | µs | |||
VCC(start) | dVCC/dt ≤ 3 V/s (see Figure 5-10) | 0.7 × V(B_IT– ) | V | |||
V(B_IT–) | dVCC/dt ≤ 3 V/s (see Figure 5-10 through Figure 5-12) | 1.71 | V | |||
Vhys(B_IT–) | dVCC/dt ≤ 3 V/s (see Figure 5-10) | 70 | 130 | 210 | mV | |
t(reset) | Pulse length needed at RST/NMI pin to accepted reset internally, VCC = 2.2 V, 3 V | 2 | µs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
t(SVSR) | dVCC/dt > 30 V/ms (see Figure 5-13) | 5 | 150 | µs | ||
dVCC/dt ≤ 30 V/ms | 2000 | |||||
td(SVSon) | SVS on, switch from VLD = 0 to VLD ≠ 0, VCC = 3 V | 150 | 300 | µs | ||
tsettle | VLD ≠ 0(2) | 12 | µs | |||
V(SVSstart) | VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 5-13) | 1.55 | 1.7 | V | ||
Vhys(SVS_IT–) | VCC/dt ≤ 3 V/s (see Figure 5-13) | VLD = 1 | 70 | 120 | 155 | mV |
VLD = 2 to 14 | V(SVS_IT–) × 0.001 | V(SVS_IT–) × 0.016 | ||||
VCC/dt ≤ 3 V/s (see Figure 5-13), external voltage applied on A7 |
VLD = 15 | 4.4 | 20 | mV | ||
V(SVS_IT–) | VCC/dt ≤ 3 V/s (see Figure 5-13) | VLD = 1 | 1.8 | 1.9 | 2.05 | V |
VLD = 2 | 1.94 | 2.1 | 2.23 | |||
VLD = 3 | 2.05 | 2.2 | 2.35 | |||
VLD = 4 | 2.14 | 2.3 | 2.46 | |||
VLD = 5 | 2.24 | 2.4 | 2.58 | |||
VLD = 6 | 2.33 | 2.5 | 2.69 | |||
VLD = 7 | 2.46 | 2.65 | 2.84 | |||
VLD = 8 | 2.58 | 2.8 | 2.97 | |||
VLD = 9 | 2.69 | 2.9 | 3.10 | |||
VLD = 10 | 2.83 | 3.05 | 3.26 | |||
VLD = 11 | 2.94 | 3.2 | 3.39 | |||
VLD = 12 | 3.11 | 3.35 | 3.58(1) | |||
VLD = 13 | 3.24 | 3.5 | 3.73(1) | |||
VLD = 14 | 3.43 | 3.7(1) | 3.96(1) | |||
VCC/dt ≤ 3 V/s (see Figure 5-13), external voltage applied on A7 |
VLD = 15 | 1.1 | 1.2 | 1.3 | ||
ICC(SVS)(3) | VLD ≠ 0, VCC = 2.2 V, 3 V | 10 | 15 | µA |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|---|
f(DCOCLK) | N(DCO) = 01Eh, FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2, DCOPLUS = 0, fCrystal = 32.738 kHz | 2.2 V, 3 V | 1 | MHz | ||
f(DCO=2) | FN_8=FN_4 = FN_3 = FN_2 = 0, DCOPLUS = 1 | 2.2 V | 0.3 | 0.65 | 1.25 | MHz |
3 V | 0.3 | 0.7 | 1.3 | |||
f(DCO=27) | FN_8 = FN_4 = FN_3 = FN_2 = 0, DCOPLUS = 1 | 2.2 V | 2.5 | 5.6 | 10.5 | MHz |
3 V | 2.7 | 6.1 | 11.3 | |||
f(DCO=2) | FN_8 = FN_4 = FN_3 = FN_2 = 1, DCOPLUS = 1 | 2.2 V | 0.7 | 1.3 | 2.3 | MHz |
3 V | 0.8 | 1.5 | 2.5 | |||
f(DCO=27) | FN_8 = FN_4 = FN_3 = FN_2 = 1, DCOPLUS = 1 | 2.2 V | 5.7 | 10.8 | 18 | MHz |
3 V | 6.5 | 12.1 | 20 | |||
f(DCO=2) | FN_8 = FN_4 = 0, FN_3 = 1, FN_2 = x, DCOPLUS = 1 | 2.2 V | 1.2 | 2 | 3 | MHz |
3 V | 1.3 | 2.2 | 3.5 | |||
f(DCO=27) | FN_8 = FN_4 = 0, FN_3 = 1, FN_2 = x, DCOPLUS = 1 | 2.2 V | 9 | 15.5 | 25 | MHz |
3 V | 10.3 | 17.9 | 28.5 | |||
f(DCO=2) | FN_8 = 0, FN_4 = 1, FN_3 = FN_2 = x, DCOPLUS = 1 | 2.2 V | 1.8 | 2.8 | 4.2 | MHz |
3 V | 2.1 | 3.4 | 5.2 | |||
f(DCO=27) | FN_8 = 0, FN_4 = 1, FN_3 = FN_2 = x, DCOPLUS = 1 | 2.2 V | 13.5 | 21.5 | 33 | MHz |
3 V | 16 | 26.6 | 41 | |||
f(DCO=2) | FN_8 = 1, FN_4 = FN_3 = FN_2 = x, DCOPLUS = 1 | 2.2 V | 2.8 | 4.2 | 6.2 | MHz |
3 V | 4.2 | 6.3 | 9.2 | |||
f(DCO=27) | FN_8 = 1, FN_4 = FN_3 = FN_2 = x, DCOPLUS = 1 | 2.2 V | 21 | 32 | 46 | MHz |
3 V | 30 | 46 | 70 | |||
Sn | Step size between adjacent DCO taps: Sn = fDCO(Tap n+1) / fDCO(Tap n) (see Figure 5-16 for taps 21 to 27) |
1 < TAP ≤ 20 | 1.06 | 1.11 | ||
TAP = 27 | 1.07 | 1.17 | ||||
Dt | Temperature drift, N(DCO) = 01Eh, FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2, DCOPLUS = 0 |
2.2 V | –0.2 | –0.3 | –0.4 | %/°C |
3 V | –0.2 | –0.3 | –0.4 | |||
DV | Drift with VCC variation, N(DCO) = 01Eh, FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2, DCOPLUS = 0 |
2.2 V, 3 V | 0 | 5 | 15 | %/V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
CXIN | Integrated input capacitance(4) | OSCCAPx = 0h, VCC = 2.2 V, 3 V | 0 | pF | ||
OSCCAPx = 1h, VCC = 2.2 V, 3 V | 10 | |||||
OSCCAPx = 2h, VCC = 2.2 V, 3 V | 14 | |||||
OSCCAPx = 3h, VCC = 2.2 V, 3 V | 18 | |||||
CXOUT | Integrated output capacitance(4) | OSCCAPx = 0h, VCC = 2.2 V, 3 V | 0 | pF | ||
OSCCAPx = 1h, VCC = 2.2 V, 3 V | 10 | |||||
OSCCAPx = 2h, VCC = 2.2 V, 3 V | 14 | |||||
OSCCAPx = 3h, VCC = 2.2 V, 3 V | 18 | |||||
VIL | Input levels at XIN | VCC = 2.2 V, 3 V(3) | VSS | 0.2 × VCC | V | |
VIH | 0.8 × VCC | VCC |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
CXT2IN | Integrated input capacitance | VCC = 2.2 V, 3 V | 2 | pF | ||
CXT2OUT | Integrated output capacitance | VCC = 2.2 V, 3 V | 2 | pF | ||
VIL | Input levels at XT2IN | VCC = 2.2 V, 3 V(2) | VSS | 0.2 × VCC | V | |
VIH | 0.8 × VCC | VCC | V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
t(τ) | USART0 deglitch time | VCC = 2.2 V, SYNC = 0, UART mode | 200 | 430 | 800 | ns |
VCC = 3 V, SYNC = 0, UART mode | 150 | 280 | 500 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
AVCC | Analog supply voltage | AVCC and DVCC are connected together, AVSS and DVSS are connected together, V(AVSS) = V(DVSS) = 0 V |
2.2 | 3.6 | V | ||
V(P6.x/Ax) | Analog input voltage range(2) | All external Ax terminals, Analog inputs selected in ADC12MCTLx register and P6Sel.x = 1, V(AVSS) ≤ VAx ≤ V(AVCC) |
0 | VAVCC | V | ||
IADC12 | Operating supply current into the AVCC terminal(3) | fADC12CLK = 5.0 MHz, ADC12ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC12DIV = 0 |
VCC = 2.2 V | 0.65 | 1.3 | mA | |
VCC = 3 V | 0.8 | 1.6 | |||||
IREF+ | Operating supply current into the AVCC terminal(4) | fADC12CLK = 5.0 MHz, ADC12ON = 0, REFON = 1, REF2_5V = 1 |
VCC = 3 V | 0.5 | 0.8 | mA | |
fADC12CLK = 5.0 MHz, ADC12ON = 0 REFON = 1, REF2_5V = 0 |
VCC = 2.2 V | 0.5 | 0.8 | mA | |||
VCC = 3 V | 0.5 | 0.8 | |||||
CI | Input capacitance | Only one terminal can be selected at one time, Ax | VCC = 2.2 V | 40 | pF | ||
RI | Input MUX ON resistance | 0 V ≤ VAx ≤ VAVCC | VCC = 3 V | 2000 | Ω |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VeREF+ | Positive external reference voltage input | VeREF+ > VREF–/VeREF–(2) | 1.4 | VAVCC | V | ||
VREF–/VeREF– | Negative external reference voltage input | VeREF+ > VREF–/VeREF–(3) | 0 | 1.2 | V | ||
(VeREF+ – VREF–/VeREF–) |
Differential external reference voltage input | VeREF+ > VREF–/VeREF–(4) | 1.4 | VAVCC | V | ||
IVeREF+ | Static input current | 0 V ≤ VeREF+ ≤ VAVCC | VCC = 2.2 V, 3 V | ±1 | µA | ||
IVREF–/VeREF– | Static input current | 0 V ≤ VeREF– ≤ VAVCC | VCC = 2.2 V, 3 V | ±1 | µA |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
VREF+ | Positive built in reference voltage output | REF2_5V = 1 for 2.5 V, IVREF+max ≤ IVREF+ ≤ IVREF+min |
3 V | 2.4 | 2.5 | 2.6 | V |
REF2_5V = 0 for 1.5 V, IVREF+max ≤ IVREF+ ≤ IVREF+min |
2.2 V, 3 V | 1.44 | 1.5 | 1.56 | |||
AVCC(min) | AVCC minimum voltage, Positive built in reference active | REF2_5V = 0, IVREF+max ≤ IVREF+ ≤ IVREF+min |
2.2 | V | |||
REF2_5V = 1, IVREF+min ≥ IVREF+ ≥ –0.5 mA |
2.8 | ||||||
REF2_5V = 1, IVREF+min ≥ IVREF+ ≥ – 1 mA |
2.9 | ||||||
IVREF+ | Load current out of VREF+ terminal | 2.2 V | 0.01 | –0.5 | mA | ||
3 V | 0.01 | –1 | |||||
IL(VREF)+ | Load-current regulation, VREF+ terminal | IVREF+ = 500 µA ± 100 µA, Analog input voltage ≈ 0.75 V, REF2_5V = 0 |
2.2 V | ±2 | LSB | ||
3 V | ±2 | ||||||
IVREF+ = 500 µA ± 100 µA, Analog input voltage ≈ 1.25 V, REF2_5V = 1 |
3 V | ±2 | LSB | ||||
IDL(VREF)+ | Load current regulation, VREF+ terminal | IVREF+ = 100 µA → 900 µA, CVREF+ = 5 µF, ax ≈ 0.5 × VREF+, Error of conversion result ≤ 1 LSB |
3 V | 20 | ns | ||
CVREF+ | Capacitance at pin VREF+(1) | REFON =1, 0 mA ≤ IVREF+ ≤ IVREF+max |
2.2 V, 3 V | 5 | 10 | µF | |
TREF+ | Temperature coefficient of built-in reference | IVREF+ is a constant in the range of 0 mA ≤ IVREF+ ≤ 1 mA |
2.2 V, 3 V | ±100 | ppm/°C | ||
tREFON | Settle time of internal reference voltage (see Figure 5-18 ) (2) | IVREF+ = 0.5 mA, CVREF+ = 10 µF, VREF+ = 1.5 V, VAVCC = 2.2 V |
17 | ms |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
fADC12CLK | ADC12 clock frequency | For specified performance of ADC12 linearity parameters | 2.2 V, 3 V | 0.45 | 5 | 6.3 | MHz |
fADC12OSC | Internal ADC12 oscillator | ADC12DIV = 0, fADC12CLK = fADC12OSC | 2.2 V, 3 V | 3.7 | 5 | 6.3 | MHz |
tCONVERT | Conversion time | CVREF+ ≥ 5 µF, Internal oscillator, fADC12OSC = 3.7 MHz to 6.3 MHz |
2.2 V, 3 V | 2.06 | 3.51 | µs | |
External fADC12CLK from ACLK, MCLK, or SMCLK, ADC12SSEL ≠ 0 | 13 × ADC12DIV × 1/fADC12CLK |
µs | |||||
tADC12ON | Turn on settling time of the ADC | See (1) | 100 | ns | |||
tSample | Sampling time | RS = 400 Ω,RI = 1000 Ω, CI = 30 pF, τ = [RS +RI] × CI(2) |
3 V | 1220 | ns | ||
2.2 V | 1400 |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
EI | Integral linearity error | 1.4 V ≤ (VeREF+ – VREF–/VeREF–) min ≤ 1.6 V | 2.2 V, 3 V | ±2 | LSB | ||
1.6 V < (VeREF+ – VREF–/VeREF–) min ≤ VAVCC | ±1.7 | ||||||
ED | Differential linearity error | (VeREF+ – VREF–/VeREF–) min ≤ (VeREF+ – VREF–/VeREF–), CVREF+ = 10 µF (tantalum) and 100 nF (ceramic) |
2.2 V, 3 V | ±1 | LSB | ||
EO | Offset error | (VeREF+ – VREF–/VeREF–) min ≤ (VeREF+ – VREF–/VeREF–), Internal impedance of source RS < 100 Ω, CVREF+ = 10 µF (tantalum) and 100 nF (ceramic) |
2.2 V, 3 V | ±2 | ±4 | LSB | |
EG | Gain error | (VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–), CVREF+ =10 µF (tantalum) and 100 nF (ceramic) |
2.2 V, 3 V | ±1.1 | ±2 | LSB | |
ET | Total unadjusted error | (VeREF+ – VREF–/VeREF– )min ≤ (VeREF+ – VREF–/VeREF–), CVREF+ = 10 µF (tantalum) and 100 nF (ceramic) |
2.2 V, 3 V | ±2 | ±5 | LSB |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
ISENSOR | Operating supply current into AVCC terminal(1) | REFON = 0, INCH = 0Ah, ADC12ON = NA, TA = 25°C |
2.2 V | 40 | 120 | µA | |
3 V | 60 | 160 | |||||
VSENSOR | See (2) | ADC12ON = 1, INCH = 0Ah, TA = 0°C |
2.2 V, 3 V | 986 | mV | ||
TCSENSOR | ADC12ON = 1, INCH = 0Ah | 2.2 V, 3 V | 3.55 ± 3% | mV/°C | |||
tSENSOR(sample) | Sample time required if channel 10 is selected(3) | ADC12ON = 1, INCH = 0Ah, Error of conversion result ≤ 1 LSB |
2.2 V | 30 | µs | ||
3 V | 30 | ||||||
IVMID | Current into divider at channel 11(4) | ADC12ON = 1, INCH = 0Bh | 2.2 V | NA | µA | ||
3 V | NA | ||||||
VMID | AVCC divider at channel 11 | ADC12ON = 1, INCH = 0Bh, VMID ≈ 0.5 × VAVCC |
2.2 V | 1.1 | 1.10 ± 0.04 | V | |
3 V | 1.5 | 1.50 ± 0.04 | |||||
tVMID(sample) | Sample time required if channel 11 is selected(5) | ADC12ON = 1, INCH = 0Bh, Error of conversion result ≤ 1 LSB |
2.2 V | 1400 | ns | ||
3 V | 1220 |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
AVCC | Analog supply voltage | AVCC = DVCC, AVSS = DVSS = 0 V | 2.2 | 3.6 | V | ||
IDD | Supply current, single DAC channel(1)(2) | DAC12AMPx = 2, DAC12IR = 0, DAC12_xDAT = 0800h |
2.2 V, 3 V | 50 | 110 | µA | |
DAC12AMPx = 2, DAC12IR = 1, DAC12_xDAT = 0800h , VeREF+ = VREF+ = AVCC |
50 | 110 | |||||
DAC12AMPx = 5, DAC12IR = 1, DAC12_xDAT = 0800h, VeREF+ = VREF+ = AVCC |
200 | 440 | |||||
DAC12AMPx = 7, DAC12IR = 1, DAC12_xDAT = 0800h, VeREF+ = VREF+ = AVCC |
700 | 1500 | |||||
PSRR | Power-supply rejection ratio(3)(4) | DAC12_xDAT = 0800h, VREF = 1.5 V, ΔAVCC = 100 mV |
2.2 V | 70 | dB | ||
DAC12_xDAT = 0800h, VREF = 1.5 V or 2.5 V, ΔAVCC = 100 mV |
3 V |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
Resolution | 12-bit monotonic | 12 | bits | ||||
INL | Integral nonlinearity(1) | Vref = 1.5 V, DAC12AMPx = 7, DAC12IR = 1 |
2.2 V | ±2.0 | ±8.0 | LSB | |
Vref = 2.5 V, DAC12AMPx = 7, DAC12IR = 1 |
3 V | ||||||
DNL | Differential nonlinearity(1) | Vref = 1.5 V, DAC12AMPx = 7, DAC12IR = 1 |
2.2 V | ±0.4 | ±1.0 | LSB | |
Vref = 2.5 V, DAC12AMPx = 7, DAC12IR = 1 |
3 V | ||||||
EO | Offset voltage without calibration(1)(2) | Vref = 1.5 V, DAC12AMPx = 7, DAC12IR = 1 |
2.2 V | ±21 | mV | ||
Vref = 2.5 V, DAC12AMPx = 7, DAC12IR = 1 |
3 V | ||||||
Offset voltage with calibration(1)(2) | Vref = 1.5 V, DAC12AMPx = 7, DAC12IR = 1 |
2.2 V | ±2.5 | ||||
Vref = 2.5 V, DAC12AMPx = 7, DAC12IR = 1 |
3 V | ||||||
dE(O)/dT | Offset error temperature coefficient(1) | 2.2 V, 3 V | ±30 | µV/°C | |||
EG | Gain error(1) | VREF = 1.5 V | 2.2 V | ±3.5 | %FSR | ||
VREF = 2.5 V | 3 V | ||||||
dE(G)/dT | Gain temperature coefficient(1) | 2.2 V, 3 V | 10 | ppm of FSR/°C |
|||
tOffset Cal | Time for offset calibration(3) | DAC12AMPx = 2 | 2.2 V, 3 V | 100 | ms | ||
DAC12AMPx = 3, 5 | 32 | ||||||
DAC12AMPx = 4, 6, 7 | 6 |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
VO | Output voltage range(1) (see Figure 5-24) | No Load, VeREF+ = AVCC, DAC12_xDAT = 0h, DAC12IR = 1, DAC12AMPx = 7 |
2.2 V, 3 V | 0 | 0.005 | V | |
No Load, VeREF+ = AVCC, DAC12_xDAT = 0FFFh, DAC12IR = 1, DAC12AMPx = 7 |
AVCC – 0.05 | AVCC | |||||
RLoad = 3 kΩ, VeREF+ = AVCC, DAC12_xDAT = 0h, DAC12IR = 1, DAC12AMPx = 7 |
0 | 0.1 | |||||
RLoad = 3 kΩ, VeREF+ = AVCC, DAC12_xDAT = 0FFFh, DAC12IR = 1, DAC12AMPx = 7 |
AVCC – 0.13 | AVCC | |||||
CL(DAC12) | Maximum DAC12 load capacitance | 2.2 V, 3 V | 100 | pF | |||
IL(DAC12) | Maximum DAC12 load current | 2.2 V | –0.5 | +0.5 | mA | ||
3 V | –1.0 | +1.0 | |||||
RO/P(DAC12) | Output resistance (see Figure 5-24) | RLoad = 3 kΩ, VO/P(DAC12) < 0.3 V, DAC12AMPx = 7, DAC12_xDAT = 0h |
2.2 V, 3 V | 150 | 250 | Ω | |
RLoad = 3 kΩ, VO/P(DAC12) > AVCC – 0.3 V, DAC12AMPx = 7, DAC12_xDAT = 0FFFh |
150 | 250 | |||||
RLoad = 3 kΩ, 0.3 V ≤ VO/P(DAC12) ≤ AVCC – 0.3 V DAC12AMPx = 7 |
1 | 4 |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
VeREF+ | Reference input voltage range | DAC12IR = 0(1)(2) | 2.2 V, 3 V | AVCC / 3 | AVCC + 0.2 | V | |
DAC12IR = 1(3)(4) | AVCC | AVCC + 0.2 | |||||
Ri(VREF+), (Ri(VeREF+) |
Reference input resistance | DAC12_0 IR = DAC12_1 IR = 0 | 2.2 V, 3 V | 20 | MΩ | ||
DAC12_0 IR = 1, DAC12_1 IR = 0 | 40 | 48 | 56 | kΩ | |||
DAC12_0 IR = 0, DAC12_1 IR = 1 | 40 | 48 | 56 | ||||
DAC12_0 IR = DAC12_1 IR =1, DAC12_0 SREFx = DAC12_1 SREFx(5) |
20 | 24 | 28 |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|---|
tON | DAC12 on time | DAC12_xDAT = 800h, ErrorV(O) < ±0.5 LSB(1) (see Figure 5-25) |
DAC12AMPx = 0 → \{2, 3, 4\} | 2.2 V, 3 V | 60 | 120 | µs | |
DAC12AMPx = 0 → \{5, 6\} | 15 | 30 | ||||||
DAC12AMPx = 0 → 7 | 6 | 12 | ||||||
tS(FS) | Settling time, full scale |
DAC12_xDAT = 80h→F7Fh→80h |
DAC12AMPx = 2 | 2.2 V, 3 V | 100 | 200 | µs | |
DAC12AMPx = 3, 5 | 40 | 80 | ||||||
DAC12AMPx = 4, 6, 7 | 15 | 30 | ||||||
tS(C–C) | Settling time, code to code |
DAC12_xDAT = 3F8h→408h→3F8h BF8h→C08h→BF8h |
DAC12AMPx = 2 | 2.2 V, 3 V | 5 | µs | ||
DAC12AMPx = 3, 5 | 2 | |||||||
DAC12AMPx = 4, 6, 7 | 1 | |||||||
SR | Slew rate | DAC12_xDAT = 80h→ F7Fh→ 80h(2) |
DAC12AMPx = 2 | 2.2 V, 3 V | 0.05 | 0.12 | V/µs | |
DAC12AMPx = 3, 5 | 0.35 | 0.7 | ||||||
DAC12AMPx = 4, 6, 7 | 1.5 | 2.7 | ||||||
Glitch energy, full scale |
DAC12_xDAT = 80h→ F7Fh→ 80h |
DAC12AMPx = 2 | 2.2 V, 3 V | 10 | nV-s | |||
DAC12AMPx = 3, 5 | 10 | |||||||
DAC12AMPx = 4, 6, 7 | 10 |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
BW–3dB | 3-dB bandwidth, VDC = 1.5 V, VAC = 0.1 VPP (see Figure 5-27) |
DAC12AMPx = \{2, 3, 4\}, DAC12SREFx = 2, DAC12IR = 1, DAC12_xDAT = 800h |
2.2 V, 3 V | 40 | kHz | ||
DAC12AMPx = \{5, 6\}, DAC12SREFx = 2, DAC12IR = 1, DAC12_xDAT = 800h |
180 | ||||||
DAC12AMPx = 7, DAC12SREFx = 2, DAC12IR = 1, DAC12_xDAT = 800h |
550 | ||||||
Channel-to-channel crosstalk(1)
(see Figure 5-28) |
DAC12_0DAT = 800h, No Load, DAC12_1DAT = 80h↔F7Fh, RLoad = 3 kΩ fDAC12_1OUT = 10 kHz with 50/50 duty cycle |
2.2 V, 3 V | –80 | dB | |||
DAC12_0DAT = 80h↔F7Fh, RLoad = 3 kΩ, DAC12_1DAT = 800h, No Load, fDAC12_0OUT = 10 kHz with 50/50 duty cycle |
–80 |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
VCC | Supply voltage | 2.2 | 3.6 | V | |||
ICC | Supply current(1) | Fast Mode, RRIP OFF | 2.2 V, 3 V | 180 | 290 | µA | |
Medium Mode, RRIP OFF | 110 | 190 | |||||
Slow Mode, RRIP OFF | 50 | 80 | |||||
Fast Mode, RRIP ON | 300 | 490 | |||||
Medium Mode, RRIP ON | 190 | 350 | |||||
Slow Mode, RRIP ON | 90 | 190 | |||||
PSRR | Power supply rejection ratio | Non-inverting | 2.2 V, 3 V | 70 | dB |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|---|
VI/P | Voltage supply, I/P | RRIP OFF | –0.1 | VCC – 1.2 | V | |||
RRIP ON | –0.1 | VCC + 0.1 | ||||||
IIkg | Input leakage current, I/P(1)(2) | TA = –40°C to +55°C | –5 | ±0.5 | 5 | nA | ||
TA = +55°C to +85°C | –20 | ±5 | 20 | |||||
Vn | Voltage noise density, I/P | Fast Mode | fV(I/P) = 1 kHz | 50 | nV/√Hz | |||
Medium Mode | 80 | |||||||
140 | ||||||||
Slow Mode | ||||||||
Fast Mode | fV(I/P) = 10 kHz | 30 | ||||||
Medium Mode | 50 | |||||||
Slow Mode | 65 | |||||||
VIO | Offset voltage, I/P | 2.2 V, 3 V | ±10 | mV | ||||
Offset temperature drift, I/P | See (3) | 2.2 V, 3 V | ±10 | µV/°C | ||||
Offset voltage drift with supply, I/P | 0.3 V ≤ VIN ≤ VCC – 0.3 V ΔVCC ≤ ±10%, TA = 25°C |
2.2 V, 3 V | ±1.5 | mV/V | ||||
VOH | High-level output voltage, O/P | Fast Mode, ISOURCE ≤ –500 µA | 2.2 V | VCC – 0.2 | VCC | V | ||
Slow Mode, ISOURCE ≤ –150 µA | 3 V | VCC – 0.1 | VCC | |||||
VOL | Low-level output voltage, O/P | Fast Mode, ISOURCE ≤ +500 µA | 2.2 V | VSS | 0.2 | V | ||
Slow Mode, ISOURCE ≤ +150 µA | 3 V | VSS | 0.1 | |||||
RO/P (OAx) | Output resistance(4) (see Figure 5-29) | RLoad = 3 kΩ,CLoad = 50 pF, RRIP ON, VO/P(OAx) < 0.2 V |
2.2 V, 3 V | 150 | 250 | Ω | ||
RLoad = 3 kΩ,CLoad = 50 pF, RRIP ON, VO/P(OAx) > AVCC – 0.2 V |
150 | 250 | ||||||
RLoad = 3 kΩ,CLoad = 50 pF, RRIP ON, 0.2 V ≤ VO/P(OAx) ≤ AVCC – 0.2 V |
||||||||
0.1 | 4 | |||||||
CMRR | Common-mode rejection ratio | Non-inverting | 2.2 V, 3 V | 70 | dB |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
SR | Slew rate | Fast Mode | 1.2 | V/µs | |||
Medium Mode | 0.8 | ||||||
Slow Mode | 0.3 | ||||||
Open-loop voltage gain | 100 | dB | |||||
φm | Phase margin | CL = 50 pF | 60 | deg | |||
Gain margin | CL = 50 pF | 20 | dB | ||||
GBW | Gain-bandwidth product (see Figure 5-30 and Figure 5-31) |
Non-inverting, Fast Mode, RL = 47 kΩ,CL = 50 pF |
2.2 V, 3 V | 2.2 | MHz | ||
1.4 | |||||||
Non-inverting, Medium Mode, RL = 300 kΩ, CL = 50 pF |
|||||||
0.5 | |||||||
Non-inverting, Slow Mode, RL = 300 kΩ, CL = 50 pF |
|||||||
ten(on) | Enable time on | ton, non-inverting, Gain = 1 | 2.2 V, 3 V | 10 | 20 | µs | |
ten(off) | Enable time off | 2.2 V, 3 V | 1 | µs |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
VCC(PGM/ ERASE) | Program and erase supply voltage | 2.7 | 3.6 | V | |||
fFTG | Flash timing generator frequency | 257 | 476 | kHz | |||
IPGM | Supply current from DVCC during program | 2.7 V, 3.6 V | 3 | 5 | mA | ||
IERASE | Supply current from DVCC during erase | 2.7 V, 3.6 V | 3 | 7 | mA | ||
tCPT | Cumulative program time | See (1) | 2.7 V, 3.6 V | 10 | ms | ||
tCMErase | Cumulative mass erase time | See (2) | 2.7 V, 3.6 V | 200 | ms | ||
Program and erase endurance | 104 | 105 | cycles | ||||
tRetention | Data retention duration | TJ = 25°C | 100 | years | |||
tWord | Word or byte program time | See (3) | 35 | tFTG | |||
tBlock, 0 | Block program time for first byte or word | 30 | |||||
tBlock, 1-63 | Block program time for each additional byte or word | 21 | |||||
tBlock, End | Block program end-sequence wait time | 6 | |||||
tMass Erase | Mass erase time | 5297 | |||||
tSeg Erase | Segment erase time | 4819 |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
fTCK | TCK input frequency | See (1) | 2.2 V | 0 | 5 | MHz | |
3 V | 0 | 10 | MHz | ||||
RInternal | Internal pullup resistance on TMS, TCK, TDI/TCLK | See (2) | 2.2 V, 3 V | 25 | 60 | 90 | kΩ |
PARAMETER | TEST CONDITIONS | MIN | MAX | UNIT | |
---|---|---|---|---|---|
VCC(FB) | Supply voltage during fuse-blow condition | TA = 25°C | 2.5 | V | |
VFB | Voltage level on TDI/TCLK for fuse-blow | 6 | 7 | V | |
IFB | Supply current into TDI/TCLK during fuse blow | 100 | mA | ||
tFB | Time to blow fuse | 1 | ms |