SLASE45E October   2014  – December 2019 MSP430FR2032 , MSP430FR2033

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
    3. 4.3 Pin Multiplexing
    4. 4.4 Connection of Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Active Mode Supply Current Per MHz
    6. 5.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode LPM3 and LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Typical Characteristics, Low-Power Mode Supply Currents
    10. 5.10 Typical Characteristics - Current Consumption Per Module
    11. 5.11 Thermal Characteristics
    12. 5.12 Timing and Switching Characteristics
      1. 5.12.1 Power Supply Sequencing
        1. Table 5-1 PMM, SVS and BOR
      2. 5.12.2 Reset Timing
        1. Table 5-2 Wake-Up Times From Low-Power Modes and Reset
      3. 5.12.3 Clock Specifications
        1. Table 5-3 XT1 Crystal Oscillator (Low Frequency)
        2. Table 5-4 DCO FLL, Frequency
        3. Table 5-5 REFO
        4. Table 5-6 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. Table 5-7 Module Oscillator Clock (MODCLK)
      4. 5.12.4 Digital I/Os
        1. Table 5-8 Digital Inputs
        2. Table 5-9 Digital Outputs
        3. 5.12.4.1  Digital I/O Typical Characteristics
      5. 5.12.5 Timer_A
        1. Table 5-10 Timer_A Recommended Operating Conditions
      6. 5.12.6 eUSCI
        1. Table 5-11 eUSCI (UART Mode) Recommended Operating Conditions
        2. Table 5-12 eUSCI (UART Mode) Switching Characteristics
        3. Table 5-13 eUSCI (SPI Master Mode) Recommended Operating Conditions
        4. Table 5-14 eUSCI (SPI Master Mode) Switching Characteristics
        5. Table 5-15 eUSCI (SPI Slave Mode) Switching Characteristics
        6. Table 5-16 eUSCI (I2C Mode) Switching Characteristics
      7. 5.12.7 ADC
        1. Table 5-17 ADC, Power Supply and Input Range Conditions
        2. Table 5-18 ADC, 10-Bit Timing Parameters
        3. Table 5-19 ADC, 10-Bit Linearity Parameters
      8. 5.12.8 FRAM
        1. Table 5-20 FRAM
      9. 5.12.9 Emulation and Debug
        1. Table 5-21 JTAG and Spy-Bi-Wire Interface Characteristics
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Operating Modes
    3. 6.3  Interrupt Vector Addresses
    4. 6.4  Bootloader (BSL)
    5. 6.5  JTAG Standard Interface
    6. 6.6  Spy-Bi-Wire Interface (SBW)
    7. 6.7  FRAM
    8. 6.8  Memory Protection
    9. 6.9  Peripherals
      1. 6.9.1  Power Management Module (PMM) and On-chip Reference Voltages
      2. 6.9.2  Clock System (CS) and Clock Distribution
      3. 6.9.3  General-Purpose Input/Output Port (I/O)
      4. 6.9.4  Watchdog Timer (WDT)
      5. 6.9.5  System Module (SYS)
      6. 6.9.6  Cyclic Redundancy Check (CRC)
      7. 6.9.7  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
      8. 6.9.8  Timers (Timer0_A3, Timer1_A3)
      9. 6.9.9  Real-Time Clock (RTC) Counter
      10. 6.9.10 10-Bit Analog Digital Converter (ADC)
      11. 6.9.11 Embedded Emulation Module (EEM)
      12. 6.9.12 Input/Output Diagrams
        1. 6.9.12.1  Port P1 Input/Output With Schmitt Trigger
        2. 6.9.12.2  Port P2 Input/Output With Schmitt Trigger
        3. 6.9.12.3  Port P3 Input/Output With Schmitt Trigger
        4. 6.9.12.4  Port P4.0 Input/Output With Schmitt Trigger
        5. 6.9.12.5  Port P4.1 and P4.2 Input/Output With Schmitt Trigger
        6. 6.9.12.6  Port 4.3, P4.4, P4.5, P4.6, and P4.7 Input/Output With Schmitt Trigger
        7. 6.9.12.7  Port P5.0, P5.1, P5.2, and P5.3 Input/Output With Schmitt Trigger
        8. 6.9.12.8  Port P5.4, P5.5, P5.6, and P5.7 Input/Output With Schmitt Trigger
        9. 6.9.12.9  Port P6.0, P6.1, P6.2, and P6.3 Input/Output With Schmitt Trigger
        10. 6.9.12.10 Port P6.4, P6.5, P6.6, and P6.7 Input/Output With Schmitt Trigger
        11. 6.9.12.11 Port P7.0, P7.1, P7.2, and P7.3 Input/Output With Schmitt Trigger
        12. 6.9.12.12 Port P7.4, P7.5, P7.6, and P7.7 Input/Output With Schmitt Trigger
        13. 6.9.12.13 Port P8.0 and P8.1 Input/Output With Schmitt Trigger
        14. 6.9.12.14 Port P8.2 and P8.3 Input/Output With Schmitt Trigger
    10. 6.10 Device Descriptors (TLV)
    11. 6.11 Memory
      1. 6.11.1 Peripheral File Map
    12. 6.12 Identification
      1. 6.12.1 Revision Identification
      2. 6.12.2 Device Identification
      3. 6.12.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Layout Guidelines
  8. 8Device and Documentation Support
    1. 8.1 Getting Started
    2. 8.2 Device Nomenclature
    3. 8.3 Tools and Sofware
    4. 8.4 Documentation Support
    5. 8.5 Related Links
    6. 8.6 Community Resources
    7. 8.7 Trademarks
    8. 8.8 Electrostatic Discharge Caution
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.2 Signal Descriptions

Table 4-1 describes the signals for all device variants and package options.

Table 4-1 Signal Descriptions

TERMINAL I/O DESCRIPTION
NAME PACKAGE SUFFIX
PM G56 G48
P4.7 1 7 7 I/O General-purpose I/O
P4.6 2 8 8 I/O General-purpose I/O
P4.5 3 9 9 I/O General-purpose I/O
P4.4 4 10 10 I/O General-purpose I/O
P4.3 5 11 11 I/O General-purpose I/O
P4.2/XOUT 6 12 12 I/O General-purpose I/O

Output terminal for crystal oscillator
P4.1/XIN 7 13 13 I/O General-purpose I/O

Input terminal for crystal oscillator
DVSS 8 14 14 Power ground
DVCC 9 15 15 Power supply
RST/NMI/SBWTDIO 10 16 16 I/O Reset input, active low

Nonmaskable interrupt input

Spy-Bi-Wire data input/output
TEST/SBWTCK 11 17 17 I Test Mode pin – selected digital I/O on JTAG pins

Spy-Bi-Wire input clock
P4.0/TA1.1 12 18 18 I/O General-purpose I/O

Timer TA1 CCR1 capture: CCI1A input, compare: Out1 outputs
P8.3/TA1.2(1) 13 19 I/O General-purpose I/O

Timer TA1 CCR2 capture: CCI2A input, compare: Out2 outputs
P8.2/TA1CLK(1) 14 20 I/O General-purpose I/O

Timer clock input TACLK for TA1
P8.1/ACLK/A9(1) 15 I/O General-purpose I/O

ACLK output

Analog input A9
P8.0/SMCLK/A8(1) 16 I/O General-purpose I/O

SMCLK output

Analog input A8
P1.7/TA0.1/TDO/A7(2) 17 21 19 I/O General-purpose I/O(2)

Timer TA0 CCR1 capture: CCI1A input, compare: Out1 outputs

Test data output

Analog input A7
P1.6/TA0.2/TDI/TCLK/A6(2) 18 22 20 I/O General-purpose I/O(2)

Timer TA0 CCR2 capture: CCI2A input, compare: Out2 outputs

Test data input or test clock input

Analog input A6
P1.5/TA0CLK/TMS/A5(2) 19 23 21 I/O General-purpose I/O(2)

Timer clock input TACLK for TA0

Test mode select

Analog input A5
P1.4/MCLK/TCK/A4/VREF+(2) 20 24 22 I/O General-purpose I/O(2)

MCLK output

Test clock

Analog input A4

Output of positive reference voltage with ground as reference
P1.3/UCA0STE/A3 21 25 23 I/O General-purpose I/O

eUSCI_A0 SPI slave transmit enable

Analog input A3
P1.2/UCA0CLK/A2 22 26 24 I/O General-purpose I/O

eUSCI_A0 SPI clock input/output

Analog input A2
P1.1/UCA0RXD/UCA0SOMI/ A1/Veref+ 23 27 25 I/O General-purpose I/O

eUSCI_A0 UART receive data

eUSCI_A0 SPI slave out/master in

Analog input A1, and ADC positive reference
P1.0/UCA0TXD/UCA0SIMO/ A0/Veref- 24 28 26 I/O General-purpose I/O

eUSCI_A0 UART transmit data

eUSCI_A0 SPI slave in/master out

Analog input A0, and ADC negative reference
P5.7(1) 25 I/O General-purpose I/O
P5.6(1) 26 I/O General-purpose I/O
P5.5(1) 27 29 I/O General-purpose I/O
P5.4(1) 28 30 I/O General-purpose I/O
P5.3/UCB0SOMI/UCB0SCL 29 31 27 I/O General-purpose I/O

eUSCI_B0 SPI slave out/master in; eUSCI_B0 I2C clock
P5.2/UCB0SIMO/UCB0SDA 30 32 28 I/O General-purpose I/O

eUSCI_B0 SPI slave in/master out; eUSCI_B0 I2C data
P5.1/UCB0CLK 31 33 29 I/O General-purpose I/O

eUSCI_B0 clock input/output
P5.0/UCB0STE 32 34 30 I/O General-purpose I/O

eUSCI_B0 slave transmit enable
P2.7 33 35 31 I/O General-purpose I/O
P2.6 34 36 32 I/O General-purpose I/O
P2.5 35 37 33 I/O General-purpose I/O
P2.4 36 38 34 I/O General-purpose I/O
P2.3 37 39 35 I/O General-purpose I/O
P2.2 38 40 36 I/O General-purpose I/O
P2.1 39 41 37 I/O General-purpose I/O
P2.0 40 42 38 I/O General-purpose I/O
P6.7(1) 41 I/O General-purpose I/O
P6.6(1) 42 I/O General-purpose I/O
P6.5(1) 43 43 I/O General-purpose I/O
P6.4(1) 44 44 I/O General-purpose I/O
P6.3 45 45 39 I/O General-purpose I/O
P6.2 46 46 40 I/O General-purpose I/O
P6.1 47 47 41 I/O General-purpose I/O
P6.0 48 48 42 I/O General-purpose I/O
P3.7 49 49 43 I/O General-purpose I/O
P3.6 50 50 44 I/O General-purpose I/O
P3.5 51 51 45 I/O General-purpose I/O
P3.4 52 52 46 I/O General-purpose I/O
P3.3 53 53 47 I/O General-purpose I/O
P3.2 54 54 48 I/O General-purpose I/O
P3.1 55 55 1 I/O General-purpose I/O
P3.0 56 56 2 I/O General-purpose I/O
P7.7(1) 57 I/O General-purpose I/O
P7.6(1) 58 I/O General-purpose I/O
P7.5(1) 59 1 I/O General-purpose I/O
P7.4(1) 60 2 I/O General-purpose I/O
P7.3 61 3 3 I/O General-purpose I/O
P7.2 62 4 4 I/O General-purpose I/O
P7.1 63 5 5 I/O General-purpose I/O
P7.0 64 6 6 I/O General-purpose I/O
(1) Any pin that is not bonded out in a smaller package must be initialized by software after reset to achieve the lowest leakage current.
(2) Because this pin is multiplexed with the JTAG function, TI recommends disabling the pin interrupt function while in JTAG debug to prevent collisions.