SLASE78D August   2016  – December 2019 MSP430FR2000 , MSP430FR2100 , MSP430FR2110 , MSP430FR2111

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Connection of Unused Pins
    6. 4.6 Buffer Type
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Active Mode Supply Current Per MHz
    6. 5.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode LPM3, LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Typical Characteristics – LPM Supply Currents
    10. 5.10 Typical Characteristics - Current Consumption Per Module
    11. 5.11 Thermal Resistance Characteristics
    12. 5.12 Timing and Switching Characteristics
      1. 5.12.1  Power Supply Sequencing
        1. Table 5-1 PMM, SVS and BOR
      2. 5.12.2  Reset Timing
        1. Table 5-2 Wake-up Times From Low-Power Modes and Reset
      3. 5.12.3  Clock Specifications
        1. Table 5-3 XT1 Crystal Oscillator (Low Frequency)
        2. Table 5-4 DCO FLL, Frequency
        3. Table 5-5 DCO Frequency
        4. Table 5-6 REFO
        5. Table 5-7 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        6. Table 5-8 Module Oscillator (MODOSC)
      4. 5.12.4  Digital I/Os
        1. Table 5-9  Digital Inputs
        2. Table 5-10 Digital Outputs
        3. 5.12.4.1   Digital I/O Typical Characteristics
      5. 5.12.5  VREF+ Built-in Reference
        1. Table 5-11 VREF+ Characteristics
      6. 5.12.6  Timer_B
        1. Table 5-12 Timer_B
      7. 5.12.7  eUSCI
        1. Table 5-13 eUSCI (UART Mode) Clock Frequency
        2. Table 5-14 eUSCI (UART Mode) Switching Characteristics
        3. Table 5-15 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-16 eUSCI (SPI Master Mode) Switching Characteristics
        5. Table 5-17 eUSCI (SPI Slave Mode) Switching Characteristics
      8. 5.12.8  ADC
        1. Table 5-18 ADC, Power Supply and Input Range Conditions
        2. Table 5-19 ADC, 10-Bit Timing Parameters
        3. Table 5-20 ADC, 10-Bit Linearity Parameters
      9. 5.12.9  Enhanced Comparator (eCOMP)
        1. Table 5-21 eCOMP
      10. 5.12.10 FRAM
        1. Table 5-22 FRAM
      11. 5.12.11 Emulation and Debug
        1. Table 5-23 JTAG, Spy-Bi-Wire Interface
        2. Table 5-24 JTAG, 4-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Memory Organization
    6. 6.6  Bootloader (BSL)
    7. 6.7  JTAG Standard Interface
    8. 6.8  Spy-Bi-Wire Interface (SBW)
    9. 6.9  FRAM
    10. 6.10 Memory Protection
    11. 6.11 Peripherals
      1. 6.11.1  Power-Management Module (PMM) and On-Chip Reference Voltages
      2. 6.11.2  Clock System (CS) and Clock Distribution
      3. 6.11.3  General-Purpose Input/Output Port (I/O)
      4. 6.11.4  Watchdog Timer (WDT)
      5. 6.11.5  System Module (SYS)
      6. 6.11.6  Cyclic Redundancy Check (CRC)
      7. 6.11.7  Enhanced Universal Serial Communication Interface (eUSCI_A0)
      8. 6.11.8  Timers (Timer0_B3)
      9. 6.11.9  Backup Memory (BAKMEM)
      10. 6.11.10 Real-Time Clock (RTC) Counter
      11. 6.11.11 10-Bit Analog-to-Digital Converter (ADC)
      12. 6.11.12 eCOMP0
      13. 6.11.13 Embedded Emulation Module (EEM)
      14. 6.11.14 Peripheral File Map
      15. 6.11.15 Input/Output Diagrams
        1. 6.11.15.1 Port P1 Input/Output With Schmitt Trigger
        2. 6.11.15.2 Port P2 Input/Output With Schmitt Trigger
    12. 6.12 Device Descriptors (TLV)
    13. 6.13 Identification
      1. 6.13.1 Revision Identification
      2. 6.13.2 Device Identification
      3. 6.13.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Layout Guidelines
    3. 7.3 Typical Applications
  8. 8Device and Documentation Support
    1. 8.1 Getting Started
    2. 8.2 Device Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Related Links
    6. 8.6 Community Resources
    7. 8.7 Trademarks
    8. 8.8 Electrostatic Discharge Caution
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Attributes

Table 4-1 lists the attributes of all pins.

Table 4-1 Pin Attributes

PIN NUMBER SIGNAL NAME(1)(4) SIGNAL TYPE(2) BUFFER TYPE(3) POWER SOURCE RESET STATE AFTER BOR(5)
PW16 RLL
1 23 P1.1 (RD) I/O LVCMOS DVCC OFF
UCA0CLK I/O LVCMOS DVCC
ACLK O LVCMOS DVCC
C1 I Analog DVCC
A1(7) I Analog DVCC
2 20 P1.0 (RD) I/O LVCMOS DVCC OFF
UCA0STE I/O LVCMOS DVCC
SMCLK O LVCMOS DVCC
C0 I Analog DVCC
A0(7) I Analog DVCC
Veref+(7) I Power DVCC
3 1 TEST (RD) I LVCMOS DVCC OFF
SBWTCK I LVCMOS DVCC
4 2 RST (RD) I/O LVCMOS DVCC OFF
NMI I LVCMOS DVCC
SBWTDIO I/O LVCMOS DVCC
5 3 DVCC P Power DVCC N/A
6 4 DVSS P Power DVCC N/A
7 5 P2.7 (RD) I/O LVCMOS DVCC OFF
TB0CLK I LVCMOS DVCC
XIN I LVCMOS DVCC
8 7 P2.6 (RD) I/O LVCMOS DVCC OFF
MCLK O LVCMOS DVCC
XOUT O LVCMOS DVCC
9 11 P2.1(RD) I/O LVCMOS DVCC OFF
TB0.2 I/O LVCMOS DVCC
10 8 P2.0 (RD) I/O LVCMOS DVCC OFF
TB0.1 I/O LVCMOS DVCC
COUT O LVCMOS DVCC
11 13 P1.7 (RD) I/O LVCMOS DVCC OFF
UCA0TXD O LVCMOS DVCC
UCA0SIMO I/O LVCMOS DVCC
TB0.2 I/O LVCMOS DVCC
TDO O LVCMOS DVCC
A7(7) I Analog DVCC
VREF+ O Power DVCC
12 14 P1.6 (RD) I/O LVCMOS DVCC OFF
UCA0RXD I LVCMOS DVCC
UCA0SOMI I/O LVCMOS DVCC
TB0.1 I/O LVCMOS DVCC
TDI I LVCMOS DVCC
TCLK I LVCMOS DVCC
A6(7) I Analog DVCC
13 15 P1.5 (RD) I/O LVCMOS DVCC OFF
UCA0CLK I/O LVCMOS DVCC
TMS I LVCMOS DVCC
A5(7) I Analog DVCC
14 16 P1.4 (RD) I/O LVCMOS DVCC OFF
UCA0STE I/O LVCMOS DVCC
TCK I LVCMOS DVCC
A4(7) I Analog DVCC
15 17 P1.3 (RD) I/O LVCMOS DVCC OFF
UCA0TXD O LVCMOS DVCC
UCA0SIMO I/O LVCMOS DVCC
C3 I Analog DVCC
A3(7) I Analog DVCC
16 19 P1.2 (RD) I/O LVCMOS DVCC OFF
UCA0RXD I LVCMOS DVCC
UCA0SOMI I/O LVCMOS DVCC
TB0TRG I LVCMOS DVCC
C2 I Analog DVCC
A2(7) I Analog DVCC
Veref-(7) I Power DVCC
6, 9, 10, 12, 18, 21, 22, 24 NC(6)
Signals names with (RD) denote the reset default pin name.
Signal Types: I = Input, O = Output, I/O = Input or Output.
Buffer Types: LVCMOS, Analog, or Power (see Section 4.6)
To determine the pin mux encodings for each pin, see Section 6.11.15.
Reset States:
OFF = High-impedance input with pullup or pulldown disabled (if available)
N/A = Not applicable
NC = Not connected
The ADC is not available on the MSP430FR2000 device.