SLASE78D August   2016  – December 2019 MSP430FR2000 , MSP430FR2100 , MSP430FR2110 , MSP430FR2111

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Connection of Unused Pins
    6. 4.6 Buffer Type
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Active Mode Supply Current Per MHz
    6. 5.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode LPM3, LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Typical Characteristics – LPM Supply Currents
    10. 5.10 Typical Characteristics - Current Consumption Per Module
    11. 5.11 Thermal Resistance Characteristics
    12. 5.12 Timing and Switching Characteristics
      1. 5.12.1  Power Supply Sequencing
        1. Table 5-1 PMM, SVS and BOR
      2. 5.12.2  Reset Timing
        1. Table 5-2 Wake-up Times From Low-Power Modes and Reset
      3. 5.12.3  Clock Specifications
        1. Table 5-3 XT1 Crystal Oscillator (Low Frequency)
        2. Table 5-4 DCO FLL, Frequency
        3. Table 5-5 DCO Frequency
        4. Table 5-6 REFO
        5. Table 5-7 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        6. Table 5-8 Module Oscillator (MODOSC)
      4. 5.12.4  Digital I/Os
        1. Table 5-9  Digital Inputs
        2. Table 5-10 Digital Outputs
        3. 5.12.4.1   Digital I/O Typical Characteristics
      5. 5.12.5  VREF+ Built-in Reference
        1. Table 5-11 VREF+ Characteristics
      6. 5.12.6  Timer_B
        1. Table 5-12 Timer_B
      7. 5.12.7  eUSCI
        1. Table 5-13 eUSCI (UART Mode) Clock Frequency
        2. Table 5-14 eUSCI (UART Mode) Switching Characteristics
        3. Table 5-15 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-16 eUSCI (SPI Master Mode) Switching Characteristics
        5. Table 5-17 eUSCI (SPI Slave Mode) Switching Characteristics
      8. 5.12.8  ADC
        1. Table 5-18 ADC, Power Supply and Input Range Conditions
        2. Table 5-19 ADC, 10-Bit Timing Parameters
        3. Table 5-20 ADC, 10-Bit Linearity Parameters
      9. 5.12.9  Enhanced Comparator (eCOMP)
        1. Table 5-21 eCOMP
      10. 5.12.10 FRAM
        1. Table 5-22 FRAM
      11. 5.12.11 Emulation and Debug
        1. Table 5-23 JTAG, Spy-Bi-Wire Interface
        2. Table 5-24 JTAG, 4-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Memory Organization
    6. 6.6  Bootloader (BSL)
    7. 6.7  JTAG Standard Interface
    8. 6.8  Spy-Bi-Wire Interface (SBW)
    9. 6.9  FRAM
    10. 6.10 Memory Protection
    11. 6.11 Peripherals
      1. 6.11.1  Power-Management Module (PMM) and On-Chip Reference Voltages
      2. 6.11.2  Clock System (CS) and Clock Distribution
      3. 6.11.3  General-Purpose Input/Output Port (I/O)
      4. 6.11.4  Watchdog Timer (WDT)
      5. 6.11.5  System Module (SYS)
      6. 6.11.6  Cyclic Redundancy Check (CRC)
      7. 6.11.7  Enhanced Universal Serial Communication Interface (eUSCI_A0)
      8. 6.11.8  Timers (Timer0_B3)
      9. 6.11.9  Backup Memory (BAKMEM)
      10. 6.11.10 Real-Time Clock (RTC) Counter
      11. 6.11.11 10-Bit Analog-to-Digital Converter (ADC)
      12. 6.11.12 eCOMP0
      13. 6.11.13 Embedded Emulation Module (EEM)
      14. 6.11.14 Peripheral File Map
      15. 6.11.15 Input/Output Diagrams
        1. 6.11.15.1 Port P1 Input/Output With Schmitt Trigger
        2. 6.11.15.2 Port P2 Input/Output With Schmitt Trigger
    12. 6.12 Device Descriptors (TLV)
    13. 6.13 Identification
      1. 6.13.1 Revision Identification
      2. 6.13.2 Device Identification
      3. 6.13.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Layout Guidelines
    3. 7.3 Typical Applications
  8. 8Device and Documentation Support
    1. 8.1 Getting Started
    2. 8.2 Device Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Related Links
    6. 8.6 Community Resources
    7. 8.7 Trademarks
    8. 8.8 Electrostatic Discharge Caution
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Revision History

Changes from revision C to revision D

Changes from August 30, 2018 to December 10, 2019

  • Changed the note that begins "Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset..." in Section 5.3, Recommended Operating ConditionsGo
  • Added the note that begins "TI recommends that power to the DVCC pin must not exceed the limits..." in Section 5.3, Recommended Operating ConditionsGo
  • Added the note that begins "A capacitor tolerance of ±20% or better is required..." in Section 5.3, Recommended Operating ConditionsGo
  • Added the note "See MSP430 32-kHz Crystal Oscillators for details on crystal section, layout, and testing" to Table 5-3, XT1 Crystal Oscillator (Low Frequency)Go
  • Changed the note that begins "Requires external capacitors at both terminals..." in Table 5-3, XT1 Crystal Oscillator (Low Frequency)Go
  • Added the t(int) parameter in Table 5-9, Digital InputsGo
  • Changed the parameter symbol from RI to RI,MUX in Table 5-18, ADC, Power Supply and Input Range ConditionsGo
  • Corrected the test conditions for the RI,MUX parameter in Table 5-18, ADC, Power Supply and Input Range ConditionsGo
  • Added RI,Misc TYP value of 34 kΩ in Table 5-18, ADC, Power Supply and Input Range ConditionsGo
  • Added tCONVERT for external ADCCLK source in Table 5-19, ADC, 10-Bit Timing ParametersGo
  • Added formula for RI in Table 5-19, ADC, 10-Bit Timing ParametersGo
  • Added the note that begins "tSample = ln(2n+1) × τ ..." in Table 5-19, ADC, 10-Bit Timing ParametersGo
  • Removed the description of "±3℃" in table note that starts "The device descriptor structure ..." of Table 5-20, ADC, 10-Bit Linearity ParametersGo
  • Corrected bitfield from IRDSEL to IRDSSEL in Section 6.11.8, Timers (Timer0_B3), in the description that starts "The interconnection of Timer0_B3 ... " Go
  • Corrected the ADCINCHx column heading in Table 6-14, ADC Channel ConnectionsGo
  • Added P1SELC information in Table 6-26, Port P1, P2 Registers (Base Address: 0200h)Go
  • Added P2SELC information in Table 6-26, Port P1, P2 Registers (Base Address: 0200h)Go

Changes from July 14, 2017 to August 29, 2018

  • Added note to VSVSH- and VSVSH+ parameters in Table 5-1, PMM, SVS and BORGo
  • Added the note "Controlled by the RTCCKSEL bit in the SYSCFG2 register" on Table 6-7, Clock DistributionGo
  • Changed 1 µF capacitor to 10 µF in Figure 7-1, Power Supply DecouplingGo
  • Updated text and figure in Section 8.2, Device NomenclatureGo

Changes from August 13, 2016 to July 13, 2017

  • Added MSP430FR2100 and MSP430FR2000 devicesGo
  • Rearranged items in Section 1.1, FeaturesGo
  • Corrected the package family for the RLL package throughout document (changed QFN to VQFN)Go
  • Upated list of applications in Section 1.2Go
  • Updated Section 1.3, DescriptionGo
  • Corrected number of bits in port P1 in Figure 1-1, Functional Block DiagramGo
  • Updated the note that starts "This is the remapped functionality controlled by the TBRMP bit..." in Table 4-2, Signal DescriptionsGo
  • Updated the note that starts "This is the remapped functionality controlled by the USCIARMP bit..." in Table 4-2, Signal DescriptionsGo
  • Removed former Figure 5-2, Low-Power Mode 3 Supply Current vs TemperatureGo
  • Updated notes on Section 5.11, Thermal Resistance CharacteristicsGo
  • Changed the entry for eUSCI_A in the LPM3 column from Off to Optional in Table 6-1, Operating ModesGo
  • Updated the note that starts "This is the remapped functionality controlled by the USCIARMP bit..." in Table 6-11, eUSCI Pin ConfigurationsGo
  • Updated the note that starts "This is the remapped functionality controlled by the TBRMP bit..." in Table 6-12, Timer0_B3 Signal ConnectionsGo
  • Removed SYSBERRIV register (not supported) from Table 6-21, SYS RegistersGo
  • Updated descriptions of "Design Kits and Evaluation Modules" in Section 8.3, Tools and SoftwareGo

Changes from August 11, 2016 to August 12, 2016

  • Changed document status from PRODUCT PREVIEW to PRODUCTION DATAGo