SLASE78D August   2016  – December 2019 MSP430FR2000 , MSP430FR2100 , MSP430FR2110 , MSP430FR2111

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Connection of Unused Pins
    6. 4.6 Buffer Type
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Active Mode Supply Current Per MHz
    6. 5.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode LPM3, LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Typical Characteristics – LPM Supply Currents
    10. 5.10 Typical Characteristics - Current Consumption Per Module
    11. 5.11 Thermal Resistance Characteristics
    12. 5.12 Timing and Switching Characteristics
      1. 5.12.1  Power Supply Sequencing
        1. Table 5-1 PMM, SVS and BOR
      2. 5.12.2  Reset Timing
        1. Table 5-2 Wake-up Times From Low-Power Modes and Reset
      3. 5.12.3  Clock Specifications
        1. Table 5-3 XT1 Crystal Oscillator (Low Frequency)
        2. Table 5-4 DCO FLL, Frequency
        3. Table 5-5 DCO Frequency
        4. Table 5-6 REFO
        5. Table 5-7 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        6. Table 5-8 Module Oscillator (MODOSC)
      4. 5.12.4  Digital I/Os
        1. Table 5-9  Digital Inputs
        2. Table 5-10 Digital Outputs
        3. 5.12.4.1   Digital I/O Typical Characteristics
      5. 5.12.5  VREF+ Built-in Reference
        1. Table 5-11 VREF+ Characteristics
      6. 5.12.6  Timer_B
        1. Table 5-12 Timer_B
      7. 5.12.7  eUSCI
        1. Table 5-13 eUSCI (UART Mode) Clock Frequency
        2. Table 5-14 eUSCI (UART Mode) Switching Characteristics
        3. Table 5-15 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-16 eUSCI (SPI Master Mode) Switching Characteristics
        5. Table 5-17 eUSCI (SPI Slave Mode) Switching Characteristics
      8. 5.12.8  ADC
        1. Table 5-18 ADC, Power Supply and Input Range Conditions
        2. Table 5-19 ADC, 10-Bit Timing Parameters
        3. Table 5-20 ADC, 10-Bit Linearity Parameters
      9. 5.12.9  Enhanced Comparator (eCOMP)
        1. Table 5-21 eCOMP
      10. 5.12.10 FRAM
        1. Table 5-22 FRAM
      11. 5.12.11 Emulation and Debug
        1. Table 5-23 JTAG, Spy-Bi-Wire Interface
        2. Table 5-24 JTAG, 4-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Memory Organization
    6. 6.6  Bootloader (BSL)
    7. 6.7  JTAG Standard Interface
    8. 6.8  Spy-Bi-Wire Interface (SBW)
    9. 6.9  FRAM
    10. 6.10 Memory Protection
    11. 6.11 Peripherals
      1. 6.11.1  Power-Management Module (PMM) and On-Chip Reference Voltages
      2. 6.11.2  Clock System (CS) and Clock Distribution
      3. 6.11.3  General-Purpose Input/Output Port (I/O)
      4. 6.11.4  Watchdog Timer (WDT)
      5. 6.11.5  System Module (SYS)
      6. 6.11.6  Cyclic Redundancy Check (CRC)
      7. 6.11.7  Enhanced Universal Serial Communication Interface (eUSCI_A0)
      8. 6.11.8  Timers (Timer0_B3)
      9. 6.11.9  Backup Memory (BAKMEM)
      10. 6.11.10 Real-Time Clock (RTC) Counter
      11. 6.11.11 10-Bit Analog-to-Digital Converter (ADC)
      12. 6.11.12 eCOMP0
      13. 6.11.13 Embedded Emulation Module (EEM)
      14. 6.11.14 Peripheral File Map
      15. 6.11.15 Input/Output Diagrams
        1. 6.11.15.1 Port P1 Input/Output With Schmitt Trigger
        2. 6.11.15.2 Port P2 Input/Output With Schmitt Trigger
    12. 6.12 Device Descriptors (TLV)
    13. 6.13 Identification
      1. 6.13.1 Revision Identification
      2. 6.13.2 Device Identification
      3. 6.13.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Layout Guidelines
    3. 7.3 Typical Applications
  8. 8Device and Documentation Support
    1. 8.1 Getting Started
    2. 8.2 Device Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Related Links
    6. 8.6 Community Resources
    7. 8.7 Trademarks
    8. 8.8 Electrostatic Discharge Caution
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Signal Descriptions

Table 4-2 describes the signals for all device variants and package options.

Table 4-2 Signal Descriptions

FUNCTION SIGNAL NAME PIN NUMBER PIN TYPE DESCRIPTION
PW16 RLL
ADC(1) A0 2 20 I Analog input A0
A1 1 23 I Analog input A1
A2 16 19 I Analog input A2
A3 15 17 I Analog input A3
A4 14 16 I Analog input A4
A5 13 15 I Analog input A5
A6 12 14 I Analog input A6
A7 11 13 I Analog input A7
Veref+ 2 20 I ADC positive reference
Veref- 16 19 I ADC negative reference
eCOMP0 C0 2 20 I Comparator input channel C0
C1 1 23 I Comparator input channel C1
C2 16 19 I Comparator input channel C2
C3 15 17 I Comparator input channel C3
COUT 10 8 O Comparator output channel COUT
Clock ACLK 1 23 O ACLK output
MCLK 8 7 O MCLK output
SMCLK 2 20 O SMCLK output
XIN 7 5 I Input terminal for crystal oscillator
XOUT 8 7 O Output terminal for crystal oscillator
Debug SBWTCK 3 1 I Spy-Bi-Wire input clock
SBWTDIO 4 2 I/O Spy-Bi-Wire data input/output
TCK 14 16 I Test clock
TCLK 12 14 I Test clock input
TDI 12 14 I Test data input
TDO 11 13 O Test data output
TMS 13 15 I Test mode select
TEST 3 1 I Test mode pin – selected digital I/O on JTAG pins
System NMI 4 2 I Nonmaskable interrupt input
RST 4 2 I/O Reset input, active low
Power DVCC 5 3 P Power supply
DVSS 6 4 P Power ground
VREF+ 11 13 P Output of positive reference voltage with ground as reference
GPIO P1.0 2 20 I/O General-purpose I/O
P1.1 1 23 I/O General-purpose I/O
P1.2 16 19 I/O General-purpose I/O
P1.3 15 17 I/O General-purpose I/O
P1.4 14 16 I/O General-purpose I/O (2)
P1.5 13 15 I/O General-purpose I/O (2)
P1.6 12 14 I/O General-purpose I/O(2)
P1.7 11 13 I/O General-purpose I/O(2)
P2.0 10 8 I/O General-purpose I/O
P2.1 9 11 I/O General-purpose I/O
P2.6 8 7 I/O General-purpose I/O
P2.7 7 5 I/O General-purpose I/O
SPI and UART UCA0CLK 13 15 I/O eUSCI_A0 SPI clock input/output
UCA0RXD 12 14 I eUSCI_A0 UART receive data
UCA0SIMO 11 13 I/O eUSCI_A0 SPI slave in/master out
UCA0SOMI 12 14 I/O eUSCI_A0 SPI slave out/master in
UCA0STE 14 16 I/O eUSCI_A0 SPI slave transmit enable
UCA0TXD 11 13 O eUSCI_A0 UART transmit data
UCA0CLK(4) 1 23 I/O eUSCI_A0 SPI clock input/output
UCA0RXD(4) 16 19 I eUSCI_A0 UART receive data
UCA0SIMO(4) 15 17 I/O eUSCI_A0 SPI slave in/master out
UCA0SOMI(4) 16 19 I/O eUSCI_A0 SPI slave out/master in
UCA0STE(4) 2 20 I/O eUSCI_A0 SPI slave transmit enable
UCA0TXD(4) 15 17 O eUSCI_A0 UART transmit data
Timer_B TB0.1 12 14 I/O Timer TB0 CCR1 capture: CCI1A input, compare: Out1 outputs
TB0.2 11 13 I/O Timer TB0 CCR2 capture: CCI2A input, compare: Out2 outputs
TB0CLK 7 5 I Timer clock input TBCLK for TB0
TB0TRG 16 19 I TB0 external trigger input for TB0OUTH
TB0.1(3) 10 8 I/O Timer TB0 CCR1 capture: CCI1A input, compare: Out1 outputs
TB0.2(3) 9 11 I/O Timer TB0 CCR2 capture: CCI2A input, compare: Out2 outputs
NC pad NC 6, 9, 10, 12, 18, 21, 22, 24 Do not connect
VQFN pad Pad Pad VQFN package (RLL) exposed thermal pad. Connect to VSS.
The ADC is not available on the MSP430FR2000 device.
Because this pin is multiplexed with the JTAG function, TI recommends disabling the pin interrupt function while in JTAG debug to prevent collisions.
This is the remapped functionality controlled by the TBRMP bit in the SYSCFG3 register. Only one selected port is valid at the same time when TB0 acts as capture input functionality. TB0 PWM outputs regardless of the setting on this remap bit.
This is the remapped functionality controlled by the USCIARMP bit in the SYSCFG3 register. Only one selected port is valid at the same time.