The Timer0_B3 module is 16-bit timer and counter with three capture/compare registers. The timer can support multiple captures or compares, PWM outputs, and interval timing (see Table 6-12). Timer0_B3 has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. The CCR0 register on Timer0_B3 is not externally connected and can be used only for hardware period timing and interrupt generation. In Up Mode, it can be used to set the overflow value of the counter.
|PORT PIN||DEVICE INPUT SIGNAL||MODULE INPUT NAME||MODULE BLOCK||MODULE OUTPUT SIGNAL||DEVICE OUTPUT SIGNAL|
|From Capacitive Touch I/O (internal)||INCLK|
|From RTC (internal)||CCI0A||CCR0||TB0|
|P1.6 (TBRMP = 0)||TB0.1||CCI1A||CCR1||TB1||TB0.1|
|P2.0 (TBRMP = 1)(1)|
|From eCOMP (internal)||CCI1B||To ADC trigger(2)|
|P1.7 (TBRMP = 0)||TB0.2||CCI2A||CCR2||TB2||TB0.2|
|P2.1 (TBRMP = 1)(1)|
|From Capacitive Touch I/O (internal)||CCI2B|
The interconnection of Timer0_B3 can be used to modulate the eUSCI_A pin of UCA0TXD/UCA0SIMO in either ASK or part of FSK mode, with which a user can easily acquire a modulated infrared command for directly driving an external IR diode. The IR functions are fully controlled by SYSCFG1 including IREN (enable), IRPSEL (polarity select), IRMSEL (mode select), IRDSSEL (data select), and IRDATA (data) bits. For more information, see the SYS chapter in the MSP430FR4xx and MSP430FR2xx Family User's Guide.
The Timer_B module can put all Timer_B outputs into a high-impedance state when the selected source is triggered. The source can be selected from external pin or internal of the device, which is controlled by TB0TRG in SYS. For more information, see the SYS chapter in the MSP430FR4xx and MSP430FR2xx Family User's Guide.
Table 6-13 summarizes the selection of the Timer_B high-impedance trigger.
|TB0TRGSEL||TB0OUTH TRIGGER SOURCE SELECTION||Timer_B PAD OUTPUT HIGH IMPEDANCE|
|TB0TRGSEL = 0||eCOMP0 output (internal)||P1.6, P1.7, P2.0, P2.1(1)|