SLASE78D August   2016  – December 2019 MSP430FR2000 , MSP430FR2100 , MSP430FR2110 , MSP430FR2111

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Connection of Unused Pins
    6. 4.6 Buffer Type
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Active Mode Supply Current Per MHz
    6. 5.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode LPM3, LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Typical Characteristics – LPM Supply Currents
    10. 5.10 Typical Characteristics - Current Consumption Per Module
    11. 5.11 Thermal Resistance Characteristics
    12. 5.12 Timing and Switching Characteristics
      1. 5.12.1  Power Supply Sequencing
        1. Table 5-1 PMM, SVS and BOR
      2. 5.12.2  Reset Timing
        1. Table 5-2 Wake-up Times From Low-Power Modes and Reset
      3. 5.12.3  Clock Specifications
        1. Table 5-3 XT1 Crystal Oscillator (Low Frequency)
        2. Table 5-4 DCO FLL, Frequency
        3. Table 5-5 DCO Frequency
        4. Table 5-6 REFO
        5. Table 5-7 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        6. Table 5-8 Module Oscillator (MODOSC)
      4. 5.12.4  Digital I/Os
        1. Table 5-9  Digital Inputs
        2. Table 5-10 Digital Outputs
        3. 5.12.4.1   Digital I/O Typical Characteristics
      5. 5.12.5  VREF+ Built-in Reference
        1. Table 5-11 VREF+ Characteristics
      6. 5.12.6  Timer_B
        1. Table 5-12 Timer_B
      7. 5.12.7  eUSCI
        1. Table 5-13 eUSCI (UART Mode) Clock Frequency
        2. Table 5-14 eUSCI (UART Mode) Switching Characteristics
        3. Table 5-15 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-16 eUSCI (SPI Master Mode) Switching Characteristics
        5. Table 5-17 eUSCI (SPI Slave Mode) Switching Characteristics
      8. 5.12.8  ADC
        1. Table 5-18 ADC, Power Supply and Input Range Conditions
        2. Table 5-19 ADC, 10-Bit Timing Parameters
        3. Table 5-20 ADC, 10-Bit Linearity Parameters
      9. 5.12.9  Enhanced Comparator (eCOMP)
        1. Table 5-21 eCOMP
      10. 5.12.10 FRAM
        1. Table 5-22 FRAM
      11. 5.12.11 Emulation and Debug
        1. Table 5-23 JTAG, Spy-Bi-Wire Interface
        2. Table 5-24 JTAG, 4-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Memory Organization
    6. 6.6  Bootloader (BSL)
    7. 6.7  JTAG Standard Interface
    8. 6.8  Spy-Bi-Wire Interface (SBW)
    9. 6.9  FRAM
    10. 6.10 Memory Protection
    11. 6.11 Peripherals
      1. 6.11.1  Power-Management Module (PMM) and On-Chip Reference Voltages
      2. 6.11.2  Clock System (CS) and Clock Distribution
      3. 6.11.3  General-Purpose Input/Output Port (I/O)
      4. 6.11.4  Watchdog Timer (WDT)
      5. 6.11.5  System Module (SYS)
      6. 6.11.6  Cyclic Redundancy Check (CRC)
      7. 6.11.7  Enhanced Universal Serial Communication Interface (eUSCI_A0)
      8. 6.11.8  Timers (Timer0_B3)
      9. 6.11.9  Backup Memory (BAKMEM)
      10. 6.11.10 Real-Time Clock (RTC) Counter
      11. 6.11.11 10-Bit Analog-to-Digital Converter (ADC)
      12. 6.11.12 eCOMP0
      13. 6.11.13 Embedded Emulation Module (EEM)
      14. 6.11.14 Peripheral File Map
      15. 6.11.15 Input/Output Diagrams
        1. 6.11.15.1 Port P1 Input/Output With Schmitt Trigger
        2. 6.11.15.2 Port P2 Input/Output With Schmitt Trigger
    12. 6.12 Device Descriptors (TLV)
    13. 6.13 Identification
      1. 6.13.1 Revision Identification
      2. 6.13.2 Device Identification
      3. 6.13.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Layout Guidelines
    3. 7.3 Typical Applications
  8. 8Device and Documentation Support
    1. 8.1 Getting Started
    2. 8.2 Device Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Related Links
    6. 8.6 Community Resources
    7. 8.7 Trademarks
    8. 8.8 Electrostatic Discharge Caution
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Timers (Timer0_B3)

The Timer0_B3 module is 16-bit timer and counter with three capture/compare registers. The timer can support multiple captures or compares, PWM outputs, and interval timing (see Table 6-12). Timer0_B3 has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. The CCR0 register on Timer0_B3 is not externally connected and can be used only for hardware period timing and interrupt generation. In Up Mode, it can be used to set the overflow value of the counter.

Table 6-12 Timer0_B3 Signal Connections

PORT PIN DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL
P2.7 TB0CLK TBCLK Timer N/A
ACLK (internal) ACLK
SMCLK (internal) SMCLK
From Capacitive Touch I/O (internal) INCLK
From RTC (internal) CCI0A CCR0 TB0
ACLK (internal) CCI0B
DVSS GND
DVCC VCC
P1.6 (TBRMP = 0) TB0.1 CCI1A CCR1 TB1 TB0.1
P2.0 (TBRMP = 1)(1)
From eCOMP (internal) CCI1B To ADC trigger(2)
DVSS GND
DVCC VCC
P1.7 (TBRMP = 0) TB0.2 CCI2A CCR2 TB2 TB0.2
P2.1 (TBRMP = 1)(1)
From Capacitive Touch I/O (internal) CCI2B
DVSS GND
DVCC VCC
This is the remapped functionality controlled by the TBRMP bit in the SYSCFG3 register. Only one selected port is valid at the same time when TB0 acts as capture input functionality. TB0 PWM outputs regardless of the setting on this remap bit.
The ADC is not available on the MSP430FR2000 device.

The interconnection of Timer0_B3 can be used to modulate the eUSCI_A pin of UCA0TXD/UCA0SIMO in either ASK or part of FSK mode, with which a user can easily acquire a modulated infrared command for directly driving an external IR diode. The IR functions are fully controlled by SYSCFG1 including IREN (enable), IRPSEL (polarity select), IRMSEL (mode select), IRDSSEL (data select), and IRDATA (data) bits. For more information, see the SYS chapter in the MSP430FR4xx and MSP430FR2xx Family User's Guide.

The Timer_B module can put all Timer_B outputs into a high-impedance state when the selected source is triggered. The source can be selected from external pin or internal of the device, which is controlled by TB0TRG in SYS. For more information, see the SYS chapter in the MSP430FR4xx and MSP430FR2xx Family User's Guide.

Table 6-13 summarizes the selection of the Timer_B high-impedance trigger.

Table 6-13 TBxOUTH

TB0TRGSEL TB0OUTH TRIGGER SOURCE SELECTION Timer_B PAD OUTPUT HIGH IMPEDANCE
TB0TRGSEL = 0 eCOMP0 output (internal) P1.6, P1.7, P2.0, P2.1(1)
TB0TRGSEL= 1 P1.2
When TB0 is set to PWM output function, both port groups can receive the output, and the output is controlled by only the PxSEL.y bits.