1.4 Functional Block Diagrams
Figure 1-1 shows the MSP430FR235x functional block diagram.
Figure 1-1 MSP430FR235x Functional Block Diagram
Figure 1-2 shows the MSP430FR215x functional block diagram.
Figure 1-2 MSP430FR215x Functional Block Diagram
- The MCU has one main power pair of DVCC and DVSS pins that supplies digital and analog modules. Recommended bypass and decoupling capacitors are 4.7 µF to 10 µF and 0.1 µF, respectively, with ±5% accuracy.
- P1, P2, P3, and P4 feature the pin-interrupt function and can wake the MCU from all LPMs, including LPM4, LPM3.5, and LPM4.5.
- Each Timer_B3 has three capture/compare registers. Only CCR1 and CCR2 are externally connected. Timer_B7 has seven capture/compare registers. Only CCR1 to CCR6 are externally connected. CCR0 registers can be used only for internal period timing and interrupt generation.
- In LPM3.5, the RTC counter and backup memory can be functional while the rest of peripherals are off.