SLASEC4C May   2018  – March 2019 MSP430FR2153 , MSP430FR2155 , MSP430FR2353 , MSP430FR2355

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagrams
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Type
    6. 4.6 Connection of Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Active Mode Supply Current Per MHz
    6. 5.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode LPM3 and LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Production Distribution of LPM3 Supply Currents
    9. 5.9  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    10. 5.10 Production Distribution of LPMx.5 Supply Currents
    11. 5.11 Typical Characteristics - Current Consumption Per Module
    12. 5.12 Thermal Resistance Characteristics
    13. 5.13 Timing and Switching Characteristics
      1. 5.13.1  Power Supply Sequencing
        1. Table 5-1 PMM, SVS and BOR
      2. 5.13.2  Reset Timing
        1. Table 5-2 Wake-up Times From Low-Power Modes and Reset
      3. 5.13.3  Clock Specifications
        1. Table 5-3 XT1 Crystal Oscillator (Low Frequency)
        2. Table 5-4 XT1 Crystal Oscillator (High Frequency)
        3. Table 5-5 DCO FLL, Frequency
        4. Table 5-6 DCO Frequency
        5. Table 5-7 REFO
        6. Table 5-8 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        7. Table 5-9 Module Oscillator (MODOSC)
      4. 5.13.4  Internal Shared Reference
        1. Table 5-10 Internal Shared Reference
      5. 5.13.5  General-Purpose I/Os
        1. Table 5-11 Digital Inputs
        2. Table 5-12 Digital Outputs
      6. 5.13.6  Digital I/O Typical Characteristics
      7. 5.13.7  Timer_B
        1. Table 5-13 Timer_B Operating Conditions
      8. 5.13.8  eUSCI
        1. Table 5-14 eUSCI (UART Mode) Clock Frequencies
        2. Table 5-15 eUSCI (UART Mode) Switching Characteristics
        3. Table 5-16 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-17 eUSCI (SPI Master Mode) Switching Characteristics
        5. Table 5-18 eUSCI (SPI Slave Mode) Switching Characteristics
        6. Table 5-19 eUSCI (I2C Mode) Switching Characteristics
      9. 5.13.9  ADC
        1. Table 5-20 ADC, Power Supply and Input Range Conditions
        2. Table 5-21 ADC, Timing Parameters
        3. Table 5-22 ADC, Linearity Parameters
      10. 5.13.10 Enhanced Comparator (eCOMP)
        1. Table 5-23 eCOMP0
        2. Table 5-24 eCOMP1
      11. 5.13.11 Smart Analog Combo (SAC) (MSP430FR235x Devices Only)
        1. Table 5-25 SAC, OA
        2. Table 5-26 SAC, DAC
      12. 5.13.12 FRAM
        1. Table 5-27 FRAM
      13. 5.13.13 Emulation and Debug
        1. Table 5-28 JTAG, Spy-Bi-Wire Interface
        2. Table 5-29 JTAG, 4-Wire Interface
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Operating Modes
    3. 6.3  Interrupt Vector Addresses
    4. 6.4  Memory Organization
    5. 6.5  Bootloader (BSL)
    6. 6.6  JTAG Standard Interface
    7. 6.7  Spy-Bi-Wire Interface (SBW)
    8. 6.8  FRAM
    9. 6.9  Memory Protection
    10. 6.10 Peripherals
      1. 6.10.1  Power Management Module (PMM) and On-Chip Reference Voltages
      2. 6.10.2  Clock System (CS) and Clock Distribution
      3. 6.10.3  General-Purpose Input/Output Port (I/O)
      4. 6.10.4  Watchdog Timer (WDT)
      5. 6.10.5  System Module (SYS)
      6. 6.10.6  Cyclic Redundancy Check (CRC)
      7. 6.10.7  Interrupt Compare Controller (ICC)
      8. 6.10.8  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_A1, eUSCI_B0, eUSCI_B1)
      9. 6.10.9  Timers (Timer0_B3, Timer1_B3, Timer2_B3, Timer3_B7)
      10. 6.10.10 Backup Memory (BKMEM)
      11. 6.10.11 Real-Time Clock (RTC) Counter
      12. 6.10.12 12-Bit Analog-to-Digital Converter (ADC)
      13. 6.10.13 Enhanced Comparator
      14. 6.10.14 Manchester Function Module (MFM)
      15. 6.10.15 Smart Analog Combo (SAC) (MSP430FR235x Devices Only)
      16. 6.10.16 eCOMP0, eCOMP1, SAC0, SAC1, SAC2, and SAC3 Interconnection (MSP430FR235x Devices Only)
      17. 6.10.17 Embedded Emulation Module (EEM)
      18. 6.10.18 Peripheral File Map
    11. 6.11 Input/Output Diagrams
      1. 6.11.1 Port P1 Input/Output With Schmitt Trigger
      2. 6.11.2 Port P2 Input/Output With Schmitt Trigger
      3. 6.11.3 Port P3 Input/Output With Schmitt Trigger
      4. 6.11.4 Port P4 Input/Output With Schmitt Trigger
      5. 6.11.5 Port P5 Input/Output With Schmitt Trigger
      6. 6.11.6 Port P6 Input/Output With Schmitt Trigger
    12. 6.12 Device Descriptors (TLV)
    13. 6.13 Identification
      1. 6.13.1 Revision Identification
      2. 6.13.2 Device Identification
      3. 6.13.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Layout Guidelines
    3. 7.3 ROM Libraries
    4. 7.4 Typical Applications
  8. 8Device and Documentation Support
    1. 8.1 Getting Started and Next Steps
    2. 8.2 Device Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Related Links
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Device Overview