SLASEO5C March   2019  – February 2020 MSP430FR2672 , MSP430FR2673 , MSP430FR2675 , MSP430FR2676

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Types
    6. 4.6 Connection of Unused Pins
  5. 5Specifications
    1. 5.1       Absolute Maximum Ratings
    2. 5.2       ESD Ratings
    3. 5.3       Recommended Operating Conditions
    4. 5.4       Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5       Active Mode Supply Current Per MHz
    6. 5.6       Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 5.7       Low-Power Mode (LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 5.8       Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 5.9       Typical Characteristics – Low-Power Mode Supply Currents
    10. Table 5-1 Typical Characteristics – Current Consumption Per Module
    11. 5.10      Thermal Resistance Characteristics
    12. 5.11      Timing and Switching Characteristics
      1. 5.11.1  Power Supply Sequencing
        1. Table 5-2 PMM, SVS and BOR
      2. 5.11.2  Reset Timing
        1. Table 5-3 Wake-up Times From Low-Power Modes and Reset
      3. 5.11.3  Clock Specifications
        1. Table 5-4 XT1 Crystal Oscillator (Low Frequency)
        2. Table 5-5 DCO FLL, Frequency
        3. Table 5-6 DCO Frequency
        4. Table 5-7 REFO
        5. Table 5-8 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        6. Table 5-9 Module Oscillator (MODOSC)
      4. 5.11.4  Digital I/Os
        1. Table 5-10 Digital Inputs
        2. Table 5-11 Digital Outputs
        3. 5.11.4.1   Typical Characteristics – Outputs at 3 V and 2 V
      5. 5.11.5  Internal Shared Reference
        1. Table 5-12 Internal Shared Reference
      6. 5.11.6  Timer_A and Timer_B
        1. Table 5-13 Timer_A
        2. Table 5-14 Timer_B
      7. 5.11.7  eUSCI
        1. Table 5-15 eUSCI (UART Mode) Clock Frequency
        2. Table 5-16 eUSCI (UART Mode)
        3. Table 5-17 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-18 eUSCI (SPI Master Mode)
        5. Table 5-19 eUSCI (SPI Slave Mode)
        6. Table 5-20 eUSCI (I2C Mode)
      8. 5.11.8  ADC
        1. Table 5-21 ADC, Power Supply and Input Range Conditions
        2. Table 5-22 ADC, Timing Parameters
        3. Table 5-23 ADC, Linearity Parameters
      9. 5.11.9  Enhanced Comparator (eCOMP)
        1. Table 5-24 eCOMP0
      10. 5.11.10 CapTIvate
        1. Table 5-25 CapTIvate Electrical Characteristics
        2. Table 5-26 CapTIvate Signal-to-Noise Ratio Characteristics
      11. 5.11.11 FRAM
        1. Table 5-27 FRAM
      12. 5.11.12 Debug and Emulation
        1. Table 5-28 JTAG, 4-Wire and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Bootloader (BSL)
    6. 6.6  JTAG Standard Interface
    7. 6.7  Spy-Bi-Wire Interface (SBW)
    8. 6.8  FRAM
    9. 6.9  Memory Protection
    10. 6.10 Peripherals
      1. 6.10.1  Power-Management Module (PMM)
      2. 6.10.2  Clock System (CS) and Clock Distribution
      3. 6.10.3  General-Purpose Input/Output Port (I/O)
      4. 6.10.4  Watchdog Timer (WDT)
      5. 6.10.5  System (SYS) Module
      6. 6.10.6  Cyclic Redundancy Check (CRC)
      7. 6.10.7  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
      8. 6.10.8  Timers (TA0, TA1, TA2, TA3 and TB0)
      9. 6.10.9  Hardware Multiplier (MPY)
      10. 6.10.10 Backup Memory (BAKMEM)
      11. 6.10.11 Real-Time Clock (RTC)
      12. 6.10.12 12-Bit Analog-to-Digital Converter (ADC)
      13. 6.10.13 eCOMP0
      14. 6.10.14 CapTIvate Technology
      15. 6.10.15 Embedded Emulation Module (EEM)
    11. 6.11 Input/Output Diagrams
      1. 6.11.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 6.11.2 Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 6.11.3 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 6.11.4 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 6.11.5 Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
      6. 6.11.6 Port P6 (P6.0 to P6.2) Input/Output With Schmitt Trigger
    12. 6.12 Device Descriptors
    13. 6.13 Memory
      1. 6.13.1 Memory Organization
      2. 6.13.2 Peripheral File Map
    14. 6.14 Identification
      1. 6.14.1 Revision Identification
      2. 6.14.2 Device Identification
      3. 6.14.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Layout Guidelines
      2. 7.2.2 CapTIvate Peripheral
        1. 7.2.2.1 Device Connection and Layout Fundamentals
        2. 7.2.2.2 Measurements
          1. 7.2.2.2.1 SNR
          2. 7.2.2.2.2 Sensitivity
          3. 7.2.2.2.3 Power
    3. 7.3 CapTIvate Technology Evaluation
  8. 8Device and Documentation Support
    1. 8.1  Getting Started and Next Steps
    2. 8.2  Device Nomenclature
    3. 8.3  Tools and Software
    4. 8.4  Documentation Support
    5. 8.5  Related Links
    6. 8.6  Support Resources
    7. 8.7  Trademarks
    8. 8.8  Electrostatic Discharge Caution
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • CapTIvate™ technology – capacitive touch
    • Performance
      • Fast electrode scanning with four simultaneous scans
      • Support for high-resolution sliders with up to 1024 points
      • Proximity sensing
    • Reliability
      • Increased immunity to power line, RF, and other environmental noise
      • Built-in spread spectrum, automatic tuning, noise filtering, and debouncing algorithms
      • Enable reliable touch solutions with 10-V RMS common-mode noise, 4-kV electrical fast transients, and 15-kV electrostatic discharge, allowing for IEC‑61000-4-6, IEC-61000-4-4, and IEC‑61000-4-2 compliance
      • Reduced RF emissions to simplify electrical designs
      • Support for metal touch and water rejection designs
    • Flexibility
    • Low power
      • <0.9 µA/button in wake-on-touch mode, where capacitive measurement and touch detection is done by hardware state machine while CPU is asleep
      • Wake-on-touch state machine allows electrode scanning while CPU sleeps
      • Hardware acceleration for environmental compensation, filtering, and threshold detection
    • Ease of use
      • CapTIvate Design Center PC GUI lets engineers design and tune capacitive buttons in real time without having to write code
      • CapTIvate software library in ROM provides ample FRAM for customer application
  • Embedded microcontroller
    • 16-bit RISC architecture
    • Clock supports frequencies up to 16 MHz
    • Wide supply voltage range from 3.6 V down to 1.8 V (minimum supply voltage is restricted by SVS levels, see the SVS Specifications)
  • Optimized ultra-low-power modes
    • Active mode: 135 µA/MHz (Typical)
    • Standby:<5 µA wake-on-touch with four sensors
    • Shutdown (LPM4.5): 37 nA without SVS
  • Low-power ferroelectric RAM (FRAM)
    • Up to 64KB of nonvolatile memory
    • Built-in error correction code (ECC)
    • Configurable write protection
    • Unified memory of program, constants, and storage
    • 1015 write cycle endurance
    • Radiation resistant and nonmagnetic
  • Intelligent digital peripherals
    • Four 16-bit timers with three capture/compare registers each (Timer_A3)
    • One 16-bit timer with seven capture/compare registers (Timer_B7)
    • One 16-bit timer associated with CapTIvate technology
    • One 16-bit counter-only RTC
    • 16-bit cyclic redundancy check (CRC)
  • Enhanced serial communications with support for pin remap feature
    • Two eUSCI_A supports UART, IrDA, and SPI
    • Two eUSCI_B supports SPI and I2C
  • High-performance analog
    • One 12-bit analog-to-digital converter (ADC) with up to 12 channels
      • Internal shared reference (1.5, 2.0, or 2.5 V)
      • Sample-and-hold 200 ksps
    • One enhanced comparator (eCOMP)
      • Integrated 6-bit DAC as reference voltage
      • Programmable hysteresis
      • Configurable high-power and low-power modes
  • Clock system (CS)
    • On-chip 32-kHz RC oscillator (REFO) with 1 µA support
    • On-chip 16-MHz digitally controlled oscillator (DCO) with frequency-locked loop (FLL)
      • ±1% accuracy with on-chip reference at room temperature
    • On-chip very low-frequency 10-kHz oscillator (VLO)
    • On-chip high-frequency modulation oscillator (MODOSC)
    • External 32-kHz crystal oscillator (LFXT)
    • Programmable MCLK prescalar of 1 to 128
    • SMCLK derived from MCLK with programmable prescalar of 1, 2, 4, or 8
  • General input/output and pin functionality
    • 43 I/Os on LQFP-48 package
    • 43 interrupt pins on all GPIOs can wake MCU from low-power modes
  • Development tools and software
  • 16KB ROM library includes CapTIvate touch libraries and driver libraries
  • Family members (also see Device Comparison)
    • MSP430FR2676: 64KB of program FRAM, 512B of information FRAM, 8KB of RAM
      supports up to 16 self-capacitive and 64 mutual-capacitive sensors
    • MSP430FR2675: 32KB of program FRAM, 512B of information FRAM, 6KB of RAM
      supports up to 16 self-capacitive and 64 mutual-capacitive sensors
    • MSP430FR2673: 16KB of program FRAM, 512B of information FRAM, 4KB of RAM
      supports up to 16 self-capacitive and 64 mutual-capacitive sensors
    • MSP430FR2672: 8KB of program FRAM, 512B of information FRAM, 2KB of RAM
      supports up to 16 self-capacitive and 24 mutual-capacitive sensors
  • Package options
    • 48-pin: LQFP (PT)
    • 40-pin: VQFN (RHA)
    • 32-pin: VQFN (RHB)